sh4_exception.h Source File
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36 #ifndef _SH3_EXCEPTION_H_
37 #define _SH3_EXCEPTION_H_
44 #define SH3_TRA 0xffffffd0
45 #define SH3_EXPEVT 0xffffffd4
46 #define SH3_INTEVT 0xffffffd8
47 #define SH7709_INTEVT2 0xa4000000
49 #define SH4_TRA 0xff000020
50 #define SH4_EXPEVT 0xff000024
51 #define SH4_INTEVT 0xff000028
57 #define EXPEVT_RESET_POWER 0x000
58 #define EXPEVT_RESET_MANUAL 0x020
59 #define EXPEVT_RESET_TLB_MULTI_HIT 0x140
62 #define EXPEVT_TLB_MISS_LD 0x040
63 #define EXPEVT_TLB_MISS_ST 0x060
64 #define EXPEVT_TLB_MOD 0x080
65 #define EXPEVT_TLB_PROT_LD 0x0a0
66 #define EXPEVT_TLB_PROT_ST 0x0c0
67 #define EXPEVT_ADDR_ERR_LD 0x0e0
68 #define EXPEVT_ADDR_ERR_ST 0x100
69 #define EXPEVT_FPU 0x120
70 #define EXPEVT_TRAPA 0x160
71 #define EXPEVT_RES_INST 0x180
72 #define EXPEVT_SLOT_INST 0x1a0
73 #define EXPEVT_BREAK 0x1e0
74 #define EXPEVT_FPU_DISABLE 0x800
75 #define EXPEVT_FPU_SLOT_DISABLE 0x820
78 #define EXP_USER 0x001
80 #define _SH_TRA_BREAK 0xc3
86 #define SH_INTEVT_NMI 0x1c0
88 #define SH_INTEVT_TMU0_TUNI0 0x400
89 #define SH_INTEVT_TMU1_TUNI1 0x420
90 #define SH_INTEVT_TMU2_TUNI2 0x440
91 #define SH_INTEVT_TMU2_TICPI2 0x460
93 #define SH_INTEVT_SCI_ERI 0x4e0
94 #define SH_INTEVT_SCI_RXI 0x500
95 #define SH_INTEVT_SCI_TXI 0x520
96 #define SH_INTEVT_SCI_TEI 0x540
98 #define SH_INTEVT_WDT_ITI 0x560
100 #define SH_INTEVT_IRL9 0x320
101 #define SH_INTEVT_IRL11 0x360
102 #define SH_INTEVT_IRL13 0x3a0
104 #define SH4_INTEVT_SCIF_ERI 0x700
105 #define SH4_INTEVT_SCIF_RXI 0x720
106 #define SH4_INTEVT_SCIF_BRI 0x740
107 #define SH4_INTEVT_SCIF_TXI 0x760
109 #define SH7709_INTEVT2_IRQ0 0x600
110 #define SH7709_INTEVT2_IRQ1 0x620
111 #define SH7709_INTEVT2_IRQ2 0x640
112 #define SH7709_INTEVT2_IRQ3 0x660
113 #define SH7709_INTEVT2_IRQ4 0x680
114 #define SH7709_INTEVT2_IRQ5 0x6a0
116 #define SH7709_INTEVT2_PINT07 0x700
117 #define SH7709_INTEVT2_PINT8F 0x720
119 #define SH7709_INTEVT2_DEI0 0x800
120 #define SH7709_INTEVT2_DEI1 0x820
121 #define SH7709_INTEVT2_DEI2 0x840
122 #define SH7709_INTEVT2_DEI3 0x860
124 #define SH7709_INTEVT2_IRDA_ERI 0x880
125 #define SH7709_INTEVT2_IRDA_RXI 0x8a0
126 #define SH7709_INTEVT2_IRDA_BRI 0x8c0
127 #define SH7709_INTEVT2_IRDA_TXI 0x8e0
129 #define SH7709_INTEVT2_SCIF_ERI 0x900
130 #define SH7709_INTEVT2_SCIF_RXI 0x920
131 #define SH7709_INTEVT2_SCIF_BRI 0x940
132 #define SH7709_INTEVT2_SCIF_TXI 0x960
134 #define SH7709_INTEVT2_ADC 0x980
137 #define SH4_INTEVT_IRL0 0x240
138 #define SH4_INTEVT_IRL1 0x2a0
139 #define SH4_INTEVT_IRL2 0x300
140 #define SH4_INTEVT_IRL3 0x360
142 #define SH4_INTEVT_IRQ0 0x200
143 #define SH4_INTEVT_IRQ1 0x220
144 #define SH4_INTEVT_IRQ2 0x240
145 #define SH4_INTEVT_IRQ3 0x260
146 #define SH4_INTEVT_IRQ4 0x280
147 #define SH4_INTEVT_IRQ5 0x2a0
148 #define SH4_INTEVT_IRQ6 0x2c0
149 #define SH4_INTEVT_IRQ7 0x2e0
150 #define SH4_INTEVT_IRQ8 0x300
151 #define SH4_INTEVT_IRQ9 0x320
152 #define SH4_INTEVT_IRQ10 0x340
153 #define SH4_INTEVT_IRQ11 0x360
154 #define SH4_INTEVT_IRQ12 0x380
155 #define SH4_INTEVT_IRQ13 0x3a0
156 #define SH4_INTEVT_IRQ14 0x3c0
157 #define SH4_INTEVT_IRQ15 0x3e0
159 #define SH4_INTEVT_TMU3 0xb00
160 #define SH4_INTEVT_TMU4 0xb80
162 #define SH4_INTEVT_PCISERR 0xa00
163 #define SH4_INTEVT_PCIERR 0xae0
164 #define SH4_INTEVT_PCIPWDWN 0xac0
165 #define SH4_INTEVT_PCIPWON 0xaa0
166 #define SH4_INTEVT_PCIDMA0 0xa80
167 #define SH4_INTEVT_PCIDMA1 0xa60
168 #define SH4_INTEVT_PCIDMA2 0xa40
169 #define SH4_INTEVT_PCIDMA3 0xa20
172 #if defined(SH3) && defined(SH4)
173 extern uint32_t __sh_TRA;
174 extern uint32_t __sh_EXPEVT;
175 extern uint32_t __sh_INTEVT;
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