arm_cpu_types.h Source File

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arm_cpu_types.h
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1 #ifndef ARM_CPU_TYPES_H
2 #define ARM_CPU_TYPES_H
3 
4 /*
5  * Copyright (C) 2005-2018 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 /* See cpu_arm.h for struct arm_cpu_type_def. */
32 /* See arm_cputypes.h for CPU_ID_xxx defines. */
33 
34 /* TODO: Refactor these flags */
35 
36 /* TODO: Include "ARM level", i.e. ARMv5 */
37 
38 
39 /* Flags: */
40 #define ARM_NO_MMU 1
41 #define ARM_DUAL_ENDIAN 2
42 #define ARM_XSCALE 4
43 
45 
46 /*
47  * NOTE: Most of these are bogus!
48  */
49 
50 #define ARM_CPU_TYPE_DEFS { \
51  { "ARM3", CPU_ID_ARM3, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \
52  { "ARM610", CPU_ID_ARM600, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \
53  { "ARM610", CPU_ID_ARM610, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \
54  { "ARM620", CPU_ID_ARM620, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \
55  \
56  { "ARM700", CPU_ID_ARM700, 0, 12, 1, 0, 1 }, \
57  { "ARM710", CPU_ID_ARM710, 0, 12, 1, 0, 1 }, \
58  { "ARM710A", CPU_ID_ARM710A, 0, 12, 1, 0, 1 }, \
59  { "ARM720T", CPU_ID_ARM720T, 0, 12, 1, 0, 1 }, \
60  { "ARM740T4K", CPU_ID_ARM740T4K,ARM_NO_MMU, 12, 1, 0, 1 }, \
61  { "ARM740T8K", CPU_ID_ARM740T8K,ARM_NO_MMU, 13, 1, 0, 1 }, \
62  { "ARM7500", CPU_ID_ARM7500, 0, 12, 1, 0, 1 }, \
63  { "ARM7500FE", CPU_ID_ARM7500FE,0, 12, 1, 0, 1 }, \
64  \
65  { "ARM810", CPU_ID_ARM810, 0, 12, 1, 0, 1 }, \
66  { "ARM920T", CPU_ID_ARM920T, 0, 14, 1, 14, 1 }, \
67  { "ARM922T", CPU_ID_ARM922T, 0, 12, 1, 0, 1 }, \
68  { "ARM940T", CPU_ID_ARM940T, ARM_NO_MMU, 12, 1, 0, 1 }, \
69  \
70  { "ARM946ES", CPU_ID_ARM946ES,ARM_NO_MMU, 12, 1, 0, 1 }, \
71  { "ARM966ES", CPU_ID_ARM966ES,ARM_NO_MMU, 12, 1, 0, 1 }, \
72  { "ARM966ESR1", CPU_ID_ARM966ESR1,ARM_NO_MMU, 12, 1, 0, 1 }, \
73  \
74  { "ARM1020E", CPU_ID_ARM1020E,0, 12, 1, 0, 1 }, \
75  { "ARM1022ES", CPU_ID_ARM1022ES,0, 12, 1, 0, 1 }, \
76  { "ARM1026EJS", CPU_ID_ARM1026EJS,0, 12, 1, 0, 1 }, \
77  { "ARM1136JS", CPU_ID_ARM1136JS,0, 12, 1, 0, 1 }, \
78  { "ARM1136JSR1",CPU_ID_ARM1136JSR1,0, 12, 1, 0, 1 }, \
79  \
80  { "SA110", CPU_ID_SA110 | 3, 0, 14, 1, 14, 1 }, \
81  { "SA1100", CPU_ID_SA1100, 0, 14, 1, 14, 1 }, \
82  { "SA1110", CPU_ID_SA1110, 0, 14, 1, 14, 1 }, \
83  \
84  { "TI925T", CPU_ID_TI925T, 0, 14, 1, 14, 1 }, \
85  { "IXP1200", CPU_ID_IXP1200, 0, 14, 1, 14, 1 }, \
86  { "80200", CPU_ID_80200, 0, 14, 1, 14, 1 }, \
87  \
88  { "PXA210", CPU_ID_PXA210, ARM_XSCALE, 16, 1, 0, 1 }, \
89  { "PXA210A", CPU_ID_PXA210A, ARM_XSCALE, 16, 1, 0, 1 }, \
90  { "PXA210B", CPU_ID_PXA210B, ARM_XSCALE, 16, 1, 0, 1 }, \
91  { "PXA210C", CPU_ID_PXA210C, ARM_XSCALE, 16, 1, 0, 1 }, \
92  { "PXA250", CPU_ID_PXA250, ARM_XSCALE, 16, 1, 0, 1 }, \
93  { "PXA250A", CPU_ID_PXA250A, ARM_XSCALE, 16, 1, 0, 1 }, \
94  { "PXA250B", CPU_ID_PXA250B, ARM_XSCALE, 16, 1, 0, 1 }, \
95  { "PXA250C", CPU_ID_PXA250C, ARM_XSCALE, 16, 1, 0, 1 }, \
96  { "PXA27X", CPU_ID_PXA27X, ARM_XSCALE, 16, 1, 0, 1 }, \
97  \
98  { "IXP425_255", CPU_ID_IXP425_266,ARM_XSCALE, 15, 1, 15, 1 }, \
99  { "IXP425_400", CPU_ID_IXP425_400,ARM_XSCALE, 15, 1, 15, 1 }, \
100  { "IXP425_533", CPU_ID_IXP425_533,ARM_XSCALE, 15, 1, 15, 1 }, \
101  \
102  { "CORTEX-A5", CPU_ID_CORTEXA5R0,0/*TODO*/, 15, 1, 15, 1 }, \
103  { "SnapdragonS2",0x511f00f2, 0/*TODO*/, 15, 1, 15, 1 }, \
104  \
105  { "80219_400", CPU_ID_80219_400,ARM_XSCALE, 15, 1, 15, 1 }, \
106  { "80219_600", CPU_ID_80219_600,ARM_XSCALE, 15, 1, 15, 1 }, \
107  { "80321_400", CPU_ID_80321_400,ARM_XSCALE, 15, 1, 15, 1 }, \
108  { "80321_400_B0",CPU_ID_80321_400_B0,ARM_XSCALE,15, 1, 15, 1 }, \
109  { "80321_600", CPU_ID_80321_600,ARM_XSCALE, 15, 1, 15, 1 }, \
110  { "80321_600_B0",CPU_ID_80321_600_B0,ARM_XSCALE,15, 1, 15, 1 }, \
111  { "80321_600_2",CPU_ID_80321_600_2,ARM_XSCALE,15, 1, 15, 1 }, \
112  \
113  { NULL, 0, 0, 0,0, 0,0 } }
114 
115 #endif /* ARM_CPU_TYPES_H */
arm_cputypes.h

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