memory_mips.cc Source File
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memory_mips.cc
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/*
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* Copyright (C) 2003-2009 Anders Gavare. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* MIPS-specific memory routines. Included from cpu_mips.c.
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*/
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#include <sys/types.h>
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#include <sys/mman.h>
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/*
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* memory_cache_R3000():
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*
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* R2000/R3000 specific cache handling.
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*
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* Return value is 1 if a jump to do_return_ok is supposed to happen directly
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* after this routine is finished, 0 otherwise.
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*/
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int
memory_cache_R3000
(
struct
cpu
*
cpu
,
int
cache, uint64_t paddr,
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int
writeflag,
size_t
len,
unsigned
char
*
data
)
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{
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unsigned
int
i;
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int
cache_isolated = 0,
addr
, hit, which_cache = cache;
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if
(len > 4 || cache ==
CACHE_NONE
)
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return
0;
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/*
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* R2000/R3000 without correct cache emulation:
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*
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* TODO: This is just enough to trick NetBSD/pmax and Ultrix into
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* being able to detect the cache sizes and think that the caches
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* are actually working, but they are not.
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*/
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if
(cache !=
CACHE_DATA
)
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return
0;
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/* Is this a cache hit or miss? */
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hit = (
cpu
->
cd
.
mips
.
cache_last_paddr
[which_cache]
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& ~
cpu
->
cd
.
mips
.
cache_mask
[which_cache])
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== (paddr & ~(
cpu
->
cd
.
mips
.
cache_mask
[which_cache]));
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/*
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* The cache miss bit is only set on cache reads, and only to the
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* data cache. (?)
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*
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* (TODO: is this correct? I don't remember where I got this from.)
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*/
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if
(cache ==
CACHE_DATA
&& writeflag==
MEM_READ
) {
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cpu
->
cd
.
mips
.
coproc
[0]->
reg
[
COP0_STATUS
] &= ~
MIPS1_CACHE_MISS
;
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if
(!hit)
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cpu
->
cd
.
mips
.
coproc
[0]->
reg
[
COP0_STATUS
] |=
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MIPS1_CACHE_MISS
;
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}
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/*
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* Is the Data cache isolated? Then don't access main memory:
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*/
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if
(cache ==
CACHE_DATA
&&
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cpu
->
cd
.
mips
.
coproc
[0]->
reg
[
COP0_STATUS
] &
MIPS1_ISOL_CACHES
)
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cache_isolated = 1;
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addr
= paddr &
cpu
->
cd
.
mips
.
cache_mask
[which_cache];
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/* Data cache isolated? Then don't access main memory: */
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if
(cache_isolated) {
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/* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
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"paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
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writeflag, cache, (uint64_t) vaddr,
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(uint64_t) paddr, addr); */
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if
(writeflag==
MEM_READ
) {
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for
(i=0; i<len; i++)
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data
[i] =
cpu
->
cd
.
mips
.
cache
[cache][(
addr
+i) &
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cpu
->
cd
.
mips
.
cache_mask
[cache]];
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}
else
{
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for
(i=0; i<len; i++)
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cpu
->
cd
.
mips
.
cache
[cache][(
addr
+i) &
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cpu
->
cd
.
mips
.
cache_mask
[cache]] =
data
[i];
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}
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return
1;
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}
else
{
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/* Reload caches if necessary: */
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/* No! Not when not emulating caches fully. (TODO?) */
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cpu
->
cd
.
mips
.
cache_last_paddr
[cache] = paddr;
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}
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return
0;
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}
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#define TRANSLATE_ADDRESS translate_v2p_mmu3k
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#define V2P_MMU3K
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#include "
memory_mips_v2p.cc
"
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#undef TRANSLATE_ADDRESS
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#undef V2P_MMU3K
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#define TRANSLATE_ADDRESS translate_v2p_mmu8k
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#define V2P_MMU8K
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#include "
memory_mips_v2p.cc
"
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#undef TRANSLATE_ADDRESS
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#undef V2P_MMU8K
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#define TRANSLATE_ADDRESS translate_v2p_mmu10k
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#define V2P_MMU10K
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#include "
memory_mips_v2p.cc
"
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#undef TRANSLATE_ADDRESS
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#undef V2P_MMU10K
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/* Almost generic :-) */
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#define TRANSLATE_ADDRESS translate_v2p_mmu4100
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#define V2P_MMU4100
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#include "
memory_mips_v2p.cc
"
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#undef TRANSLATE_ADDRESS
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#undef V2P_MMU4100
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#define TRANSLATE_ADDRESS translate_v2p_generic
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#include "
memory_mips_v2p.cc
"
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mips_coproc::reg
uint64_t reg[N_MIPS_COPROC_REGS]
Definition:
cpu_mips.h:102
data
u_short data
Definition:
siireg.h:79
mips_cpu::coproc
struct mips_coproc * coproc[N_MIPS_COPROCS]
Definition:
cpu_mips.h:219
memory_mips_v2p.cc
mips_cpu::cache_mask
int cache_mask[2]
Definition:
cpu_mips.h:272
MEM_READ
#define MEM_READ
Definition:
memory.h:116
addr
uint32_t addr
Definition:
tmp_arm_multi.cc:52
mips_cpu::cache_last_paddr
uint64_t cache_last_paddr[2]
Definition:
cpu_mips.h:269
MIPS1_ISOL_CACHES
#define MIPS1_ISOL_CACHES
Definition:
mips_cpuregs.h:180
cpu::mips
struct mips_cpu mips
Definition:
cpu.h:446
memory_cache_R3000
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data)
Definition:
memory_mips.cc:43
MIPS1_CACHE_MISS
#define MIPS1_CACHE_MISS
Definition:
mips_cpuregs.h:177
CACHE_NONE
#define CACHE_NONE
Definition:
memory.h:123
cpu::cd
union cpu::@1 cd
mips_cpu::cache
unsigned char * cache[2]
Definition:
cpu_mips.h:267
CACHE_DATA
#define CACHE_DATA
Definition:
memory.h:121
cpu
Definition:
cpu.h:326
COP0_STATUS
#define COP0_STATUS
Definition:
cop0.h:109
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