z8530reg.h Source File
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94 #define ZSRR_SDLC_ADDR 6
95 #define ZSRR_SDLC_FLAG 7
96 #define ZSRR_BAUDLO 12
97 #define ZSRR_BAUDHI 13
98 #define ZSRR_ENHANCED 14
101 #define ZSWR_TXSYNC 6
102 #define ZSWR_RXSYNC 7
103 #define ZSWR_SYNCLO 6
104 #define ZSWR_SYNCHI 7
105 #define ZSWR_SDLC_ADDR 6
106 #define ZSWR_SDLC_FLAG 7
107 #define ZSWR_BAUDLO 12
108 #define ZSWR_BAUDHI 13
109 #define ZSWR_ENHANCED 7
119 #define ZSM_RESET_TXUEOM 0xc0
120 #define ZSM_RESET_TXCRC 0x80
121 #define ZSM_RESET_RXCRC 0x40
122 #define ZSM_NULL 0x00
124 #define ZSM_RESET_IUS 0x38
125 #define ZSM_RESET_ERR 0x30
126 #define ZSM_RESET_TXINT 0x28
127 #define ZSM_EI_NEXTRXC 0x20
128 #define ZSM_SEND_ABORT 0x18
129 #define ZSM_RESET_STINT 0x10
130 #define ZSM_POINTHIGH 0x08
131 #define ZSM_NULL 0x00
138 #define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM
139 #define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC
140 #define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC
141 #define ZSWR0_CLR_INTR ZSM_RESET_IUS
142 #define ZSWR0_RESET_ERRORS ZSM_RESET_ERR
143 #define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC
144 #define ZSWR0_SEND_ABORT ZSM_SEND_ABORT
145 #define ZSWR0_RESET_STATUS ZSM_RESET_STINT
146 #define ZSWR0_RESET_TXINT ZSM_RESET_TXINT
153 #define ZSWR1_REQ_WAIT 0x80
154 #define ZSWR1_REQ_REQ 0xc0
155 #define ZSWR1_REQ_TX 0x00
156 #define ZSWR1_REQ_RX 0x20
158 #define ZSWR1_RIE_NONE 0x00
159 #define ZSWR1_RIE_FIRST 0x08
160 #define ZSWR1_RIE 0x10
161 #define ZSWR1_RIE_SPECIAL_ONLY 0x18
163 #define ZSWR1_PE_SC 0x04
164 #define ZSWR1_TIE 0x02
165 #define ZSWR1_SIE 0x01
167 #define ZSWR1_IMASK 0x1F
170 #define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX)
181 #define ZSWR3_RX_5 0x00
182 #define ZSWR3_RX_7 0x40
183 #define ZSWR3_RX_6 0x80
184 #define ZSWR3_RX_8 0xc0
185 #define ZSWR3_RXSIZE 0xc0
187 #define ZSWR3_HFC 0x20
188 #define ZSWR3_HUNT 0x10
189 #define ZSWR3_RXCRC_ENABLE 0x08
190 #define ZSWR3_ADDR_SEARCH_MODE 0x04
191 #define ZSWR3_SDLC_SHORT_ADDR 0x02
192 #define ZSWR3_SYNC_LOAD_INH 0x02
193 #define ZSWR3_RX_ENABLE 0x01
199 #define ZSWR4_CLK_X1 0x00
200 #define ZSWR4_CLK_X16 0x40
201 #define ZSWR4_CLK_X32 0x80
202 #define ZSWR4_CLK_X64 0xc0
203 #define ZSWR4_CLK_MASK 0xc0
205 #define ZSWR4_MONOSYNC 0x00
206 #define ZSWR4_BISYNC 0x10
207 #define ZSWR4_SDLC 0x20
208 #define ZSWR4_EXTSYNC 0x30
209 #define ZSWR4_SYNC_MASK 0x30
211 #define ZSWR4_SYNCMODE 0x00
212 #define ZSWR4_ONESB 0x04
213 #define ZSWR4_1P5SB 0x08
214 #define ZSWR4_TWOSB 0x0c
215 #define ZSWR4_SBMASK 0x0c
217 #define ZSWR4_EVENP 0x02
218 #define ZSWR4_PARENB 0x01
219 #define ZSWR4_PARMASK 0x03
226 #define ZSWR5_DTR 0x80
228 #define ZSWR5_TX_5 0x00
229 #define ZSWR5_TX_7 0x20
230 #define ZSWR5_TX_6 0x40
231 #define ZSWR5_TX_8 0x60
232 #define ZSWR5_TXSIZE 0x60
234 #define ZSWR5_BREAK 0x10
235 #define ZSWR5_TX_ENABLE 0x08
236 #define ZSWR5_CRC16 0x04
237 #define ZSWR5_RTS 0x02
238 #define ZSWR5_TXCRC_ENABLE 0x01
244 #define ZSWR7_SDLCFLAG 0x7e
254 #define ZSWR7P_EXTEND_READ 0x40
255 #define ZSWR7P_TX_FIFO 0x20
256 #define ZSWR7P_DTR_TIME 0x10
257 #define ZSWR7P_RX_FIFO 0x08
258 #define ZSWR7P_RTS_DEACT 0x04
259 #define ZSWR7P_AUTO_EOM_RESET 0x02
260 #define ZSWR7P_AUTO_TX_FLAG 0x01
267 #define ZSWR9_HARD_RESET 0xc0
268 #define ZSWR9_A_RESET 0x80
269 #define ZSWR9_B_RESET 0x40
270 #define ZSWR9_SOFT_INTAC 0x20
272 #define ZSWR9_STATUS_HIGH 0x10
273 #define ZSWR9_MASTER_IE 0x08
274 #define ZSWR9_DLC 0x04
275 #define ZSWR9_NO_VECTOR 0x02
276 #define ZSWR9_VECTOR_INCL_STAT 0x01
283 #define ZSWR10_PRESET_ONES 0x80
285 #define ZSWR10_NRZ 0x00
286 #define ZSWR10_NRZI 0x20
287 #define ZSWR10_FM1 0x40
288 #define ZSWR10_FM0 0x60
290 #define ZSWR10_GA_ON_POLL 0x10
291 #define ZSWR10_MARK_IDLE 0x08
292 #define ZSWR10_ABORT_ON_UNDERRUN 0x4
293 #define ZSWR10_LOOP_MODE 0x02
294 #define ZSWR10_6_BIT_SYNC 0x01
301 #define ZSWR11_XTAL 0x80
303 #define ZSWR11_RXCLK_RTXC 0x00
304 #define ZSWR11_RXCLK_TRXC 0x20
305 #define ZSWR11_RXCLK_BAUD 0x40
306 #define ZSWR11_RXCLK_DPLL 0x60
308 #define ZSWR11_TXCLK_RTXC 0x00
309 #define ZSWR11_TXCLK_TRXC 0x08
310 #define ZSWR11_TXCLK_BAUD 0x10
311 #define ZSWR11_TXCLK_DPLL 0x18
313 #define ZSWR11_TRXC_OUT_ENA 0x04
315 #define ZSWR11_TRXC_XTAL 0x00
316 #define ZSWR11_TRXC_XMIT 0x01
317 #define ZSWR11_TRXC_BAUD 0x02
318 #define ZSWR11_TRXC_DPLL 0x03
341 #define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2)
344 #define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2))
350 #define ZSWR14_DPLL_NOOP 0x00
351 #define ZSWR14_DPLL_SEARCH 0x20
352 #define ZSWR14_DPLL_RESET_CM 0x40
353 #define ZSWR14_DPLL_DISABLE 0x60
354 #define ZSWR14_DPLL_SRC_BAUD 0x80
355 #define ZSWR14_DPLL_SRC_RTXC 0xa0
356 #define ZSWR14_DPLL_FM 0xc0
357 #define ZSWR14_DPLL_NRZI 0xe0
359 #define ZSWR14_LOCAL_LOOPBACK 0x10
360 #define ZSWR14_AUTO_ECHO 0x08
361 #define ZSWR14_DTR_REQ 0x04
362 #define ZSWR14_BAUD_FROM_PCLK 0x02
364 #define ZSWR14_BAUD_ENA 0x01
375 #define ZSWR15_BREAK_IE 0x80
376 #define ZSWR15_TXUEOM_IE 0x40
377 #define ZSWR15_CTS_IE 0x20
378 #define ZSWR15_SYNCHUNT_IE 0x10
379 #define ZSWR15_DCD_IE 0x08
380 #define ZSWR15_SDLC_FIFO 0x04
381 #define ZSWR15_ZERO_COUNT_IE 0x02
382 #define ZSWR15_ENABLE_ENHANCED 0x01
388 #define ZSRR0_BREAK 0x80
389 #define ZSRR0_TXUNDER 0x40
390 #define ZSRR0_CTS 0x20
391 #define ZSRR0_SYNC_HUNT 0x10
392 #define ZSRR0_DCD 0x08
393 #define ZSRR0_TX_READY 0x04
394 #define ZSRR0_ZERO_COUNT 0x02
395 #define ZSRR0_RX_READY 0x01
400 #define ZSRR1_EOF 0x80
401 #define ZSRR1_FE 0x40
402 #define ZSRR1_DO 0x20
403 #define ZSRR1_PE 0x10
404 #define ZSRR1_RC0 0x08
405 #define ZSRR1_RC1 0x04
406 #define ZSRR1_RC2 0x02
407 #define ZSRR1_ALL_SENT 0x01
420 #define ZSRR3_IP_A_RX 0x20
421 #define ZSRR3_IP_A_TX 0x10
422 #define ZSRR3_IP_A_STAT 0x08
423 #define ZSRR3_IP_B_RX 0x04
424 #define ZSRR3_IP_B_TX 0x02
425 #define ZSRR3_IP_B_STAT 0x01
430 #define ZSRR10_1_CLOCK_MISSING 0x80
431 #define ZSRR10_2_CLOCKS_MISSING 0x40
433 #define ZSRR10_LOOP_SENDING 0x10
436 #define ZSRR10_ON_LOOP 0x02
442 #define ZSRR15_BREAK_IE 0x80
443 #define ZSRR15_TXUEOM_IE 0x40
444 #define ZSRR15_CTS_IE 0x20
445 #define ZSRR15_SYNCHUNT_IE 0x10
446 #define ZSRR15_DCD_IE 0x08
448 #define ZSRR15_ZERO_COUNT_IE 0x02
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