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Macros | |
#define | YAMON_FUNCTION_BASE 0x1fc00500 |
#define | YAMON_PRINT_COUNT_OFS (YAMON_FUNCTION_BASE + 0x04) |
#define | YAMON_EXIT_OFS (YAMON_FUNCTION_BASE + 0x20) |
#define | YAMON_FLUSH_CACHE_OFS (YAMON_FUNCTION_BASE + 0x2c) |
#define | YAMON_PRINT_OFS (YAMON_FUNCTION_BASE + 0x34) |
#define | YAMON_REG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x38) |
#define | YAMON_DEREG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x3c) |
#define | YAMON_REG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x40) |
#define | YAMON_DEREG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x44) |
#define | YAMON_REG_ESR_OFS (YAMON_FUNCTION_BASE + 0x48) |
#define | YAMON_DEREG_ESR_OFS (YAMON_FUNCTION_BASE + 0x4c) |
#define | YAMON_GETCHAR_OFS (YAMON_FUNCTION_BASE + 0x50) |
#define | YAMON_SYSCON_READ_OFS (YAMON_FUNCTION_BASE + 0x54) |
#define | SYSCON_BOARD_CPU_CLOCK_FREQ_ID 34 /* UINT32 */ |
#define | SYSCON_BOARD_BUS_CLOCK_FREQ_ID 35 /* UINT32 */ |
#define | SYSCON_BOARD_PCI_FREQ_KHZ_ID 36 /* UINT32 */ |
#define YAMON_DEREG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x3c) |
#define YAMON_DEREG_ESR_OFS (YAMON_FUNCTION_BASE + 0x4c) |
#define YAMON_DEREG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x44) |
#define YAMON_EXIT_OFS (YAMON_FUNCTION_BASE + 0x20) |
#define YAMON_FLUSH_CACHE_OFS (YAMON_FUNCTION_BASE + 0x2c) |
#define YAMON_GETCHAR_OFS (YAMON_FUNCTION_BASE + 0x50) |
#define YAMON_PRINT_COUNT_OFS (YAMON_FUNCTION_BASE + 0x04) |
#define YAMON_PRINT_OFS (YAMON_FUNCTION_BASE + 0x34) |
#define YAMON_REG_CPU_ISR_OFS (YAMON_FUNCTION_BASE + 0x38) |
#define YAMON_REG_ESR_OFS (YAMON_FUNCTION_BASE + 0x48) |
#define YAMON_REG_IC_ISR_OFS (YAMON_FUNCTION_BASE + 0x40) |
#define YAMON_SYSCON_READ_OFS (YAMON_FUNCTION_BASE + 0x54) |