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Macros | |
#define | IIC_ICR 0x00 /* i2c control register */ |
#define | IIC_ISR 0x04 /* i2c status register */ |
#define | IIC_ISAR 0x08 /* i2c slave address register */ |
#define | IIC_IDBR 0x0c /* i2c data buffer register */ |
#define | IIC_ICCR 0x10 /* i2c clock control register (i80312 only) */ |
#define | IIC_IBMR 0x14 /* i2c bus monitor register */ |
#define | IIC_ICR_FM (1U << 15) /* fast mode (i80321 only) */ |
#define | IIC_ICR_RESET (1U << 14) /* i2c unit reset */ |
#define | IIC_ICR_SADIE (1U << 13) /* slave addr det int en */ |
#define | IIC_ICR_ALDIE (1U << 12) /* arb loss det int en */ |
#define | IIC_ICR_SSDIE (1U << 11) /* slave stop det in en */ |
#define | IIC_ICR_BEIE (1U << 10) /* bus error int en */ |
#define | IIC_ICR_IRFIE (1U << 9) /* IDBR Rx full int en */ |
#define | IIC_ICR_ITEIE (1U << 8) /* IDBR Tx empty int en */ |
#define | IIC_ICR_GCD (1U << 7) /* general call disable */ |
#define | IIC_ICR_UE (1U << 6) /* i2c unit enable */ |
#define | IIC_ICR_SCLE (1U << 5) /* SCL master enable */ |
#define | IIC_ICR_MA (1U << 4) /* abort as master */ |
#define | IIC_ICR_TB (1U << 3) /* transfer byte */ |
#define | IIC_ICR_NACK (1U << 2) /* 0=ACK, 1=NACK */ |
#define | IIC_ICR_STOP (1U << 1) /* initiate STOP condition */ |
#define | IIC_ICR_START (1U << 0) /* initiate START condition */ |
#define | IIC_ISR_BED (1U << 10) /* bus error detected */ |
#define | IIC_ISR_SAD (1U << 9) /* slave address detected */ |
#define | IIC_ISR_GCAD (1U << 8) /* general call addr detected */ |
#define | IIC_ISR_IRF (1U << 7) /* IDBR Rx full */ |
#define | IIC_ISR_ITE (1U << 6) /* IDBR Tx empty */ |
#define | IIC_ISR_ALD (1U << 5) /* arb loss detected */ |
#define | IIC_ISR_SSD (1U << 4) /* slave STOP detected */ |
#define | IIC_ISR_IBB (1U << 3) /* i2c bus busy */ |
#define | IIC_ISR_UB (1U << 2) /* unit busy */ |
#define | IIC_ISR_NACK (1U << 1) /* NACK received */ |
#define | IIC_ISR_RW (1U << 0) /* 0=mt/sr, 1=mr/st */ |
#define IIC_IBMR 0x14 /* i2c bus monitor register */ |
Definition at line 47 of file iopi2creg.h.
#define IIC_ICCR 0x10 /* i2c clock control register (i80312 only) */ |
Definition at line 46 of file iopi2creg.h.
#define IIC_ICR 0x00 /* i2c control register */ |
Definition at line 42 of file iopi2creg.h.
#define IIC_ICR_ALDIE (1U << 12) /* arb loss det int en */ |
Definition at line 52 of file iopi2creg.h.
#define IIC_ICR_BEIE (1U << 10) /* bus error int en */ |
Definition at line 54 of file iopi2creg.h.
#define IIC_ICR_FM (1U << 15) /* fast mode (i80321 only) */ |
Definition at line 49 of file iopi2creg.h.
#define IIC_ICR_GCD (1U << 7) /* general call disable */ |
Definition at line 57 of file iopi2creg.h.
#define IIC_ICR_IRFIE (1U << 9) /* IDBR Rx full int en */ |
Definition at line 55 of file iopi2creg.h.
#define IIC_ICR_ITEIE (1U << 8) /* IDBR Tx empty int en */ |
Definition at line 56 of file iopi2creg.h.
#define IIC_ICR_MA (1U << 4) /* abort as master */ |
Definition at line 60 of file iopi2creg.h.
#define IIC_ICR_NACK (1U << 2) /* 0=ACK, 1=NACK */ |
Definition at line 62 of file iopi2creg.h.
#define IIC_ICR_RESET (1U << 14) /* i2c unit reset */ |
Definition at line 50 of file iopi2creg.h.
Definition at line 51 of file iopi2creg.h.
#define IIC_ICR_SCLE (1U << 5) /* SCL master enable */ |
Definition at line 59 of file iopi2creg.h.
#define IIC_ICR_SSDIE (1U << 11) /* slave stop det in en */ |
Definition at line 53 of file iopi2creg.h.
#define IIC_ICR_START (1U << 0) /* initiate START condition */ |
Definition at line 64 of file iopi2creg.h.
#define IIC_ICR_STOP (1U << 1) /* initiate STOP condition */ |
Definition at line 63 of file iopi2creg.h.
#define IIC_ICR_TB (1U << 3) /* transfer byte */ |
Definition at line 61 of file iopi2creg.h.
#define IIC_ICR_UE (1U << 6) /* i2c unit enable */ |
Definition at line 58 of file iopi2creg.h.
#define IIC_IDBR 0x0c /* i2c data buffer register */ |
Definition at line 45 of file iopi2creg.h.
#define IIC_ISAR 0x08 /* i2c slave address register */ |
Definition at line 44 of file iopi2creg.h.
#define IIC_ISR 0x04 /* i2c status register */ |
Definition at line 43 of file iopi2creg.h.
#define IIC_ISR_ALD (1U << 5) /* arb loss detected */ |
Definition at line 71 of file iopi2creg.h.
#define IIC_ISR_BED (1U << 10) /* bus error detected */ |
Definition at line 66 of file iopi2creg.h.
Definition at line 68 of file iopi2creg.h.
#define IIC_ISR_IBB (1U << 3) /* i2c bus busy */ |
Definition at line 73 of file iopi2creg.h.
#define IIC_ISR_IRF (1U << 7) /* IDBR Rx full */ |
Definition at line 69 of file iopi2creg.h.
#define IIC_ISR_ITE (1U << 6) /* IDBR Tx empty */ |
Definition at line 70 of file iopi2creg.h.
#define IIC_ISR_NACK (1U << 1) /* NACK received */ |
Definition at line 75 of file iopi2creg.h.
#define IIC_ISR_RW (1U << 0) /* 0=mt/sr, 1=mr/st */ |
Definition at line 76 of file iopi2creg.h.
#define IIC_ISR_SAD (1U << 9) /* slave address detected */ |
Definition at line 67 of file iopi2creg.h.
#define IIC_ISR_SSD (1U << 4) /* slave STOP detected */ |
Definition at line 72 of file iopi2creg.h.
#define IIC_ISR_UB (1U << 2) /* unit busy */ |
Definition at line 74 of file iopi2creg.h.