cpu_arm.h Source File
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59 #define ARM_REG_NAMES { \
60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
63 #define ARM_CONDITION_STRINGS { \
64 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65 "hi", "ls", "ge", "lt", "gt", "le", "" , "(INVALID)" }
68 #define ARM_DPI_NAMES { \
69 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70 "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
72 #define ARM_THUMB_DPI_NAMES { \
73 "ands", "eors", "lsls", "lsrs", "asrs", "adcs", "sbcs", "rors", \
74 "tst", "negs", "cmp", "cmn", "orrs", "muls", "bics", "mvns" }
76 #define ARM_IC_ENTRIES_SHIFT 10
78 #define ARM_N_IC_ARGS 3
79 #define ARM_INSTR_ALIGNMENT_SHIFT 2
80 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81 #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82 & (ARM_IC_ENTRIES_PER_PAGE-1))
83 #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84 + ARM_INSTR_ALIGNMENT_SHIFT))
91 #define ARM_FLAG_N 0x80000000
92 #define ARM_FLAG_Z 0x40000000
93 #define ARM_FLAG_C 0x20000000
94 #define ARM_FLAG_V 0x10000000
95 #define ARM_FLAG_Q 0x08000000
96 #define ARM_FLAG_J 0x01000000
97 #define ARM_FLAG_E 0x00000200
98 #define ARM_FLAG_A 0x00000100
99 #define ARM_FLAG_I 0x00000080
100 #define ARM_FLAG_F 0x00000040
101 #define ARM_FLAG_T 0x00000020
103 #define ARM_FLAG_MODE 0x0000001f
104 #define ARM_MODE_USR26 0x00
105 #define ARM_MODE_FIQ26 0x01
106 #define ARM_MODE_IRQ26 0x02
107 #define ARM_MODE_SVC26 0x03
108 #define ARM_MODE_USR32 0x10
109 #define ARM_MODE_FIQ32 0x11
110 #define ARM_MODE_IRQ32 0x12
111 #define ARM_MODE_SVC32 0x13
112 #define ARM_MODE_ABT32 0x17
113 #define ARM_MODE_UND32 0x1b
114 #define ARM_MODE_SYS32 0x1f
116 #define ARM_EXCEPTION_TO_MODE { \
117 ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
118 ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
120 #define N_ARM_EXCEPTIONS 8
122 #define ARM_EXCEPTION_RESET 0
123 #define ARM_EXCEPTION_UND 1
124 #define ARM_EXCEPTION_SWI 2
125 #define ARM_EXCEPTION_PREF_ABT 3
126 #define ARM_EXCEPTION_DATA_ABT 4
128 #define ARM_EXCEPTION_IRQ 6
129 #define ARM_EXCEPTION_FIQ 7
133 #define ARM_MAX_VPH_TLB_ENTRIES 384
144 int opcode2,
int l_bit,
int crn,
int crm,
257 #define ARM_CONTROL_MMU 0x0001
258 #define ARM_CONTROL_ALIGN 0x0002
259 #define ARM_CONTROL_CACHE 0x0004
260 #define ARM_CONTROL_WBUFFER 0x0008
261 #define ARM_CONTROL_PROG32 0x0010
262 #define ARM_CONTROL_DATA32 0x0020
263 #define ARM_CONTROL_BIG 0x0080
264 #define ARM_CONTROL_S 0x0100
265 #define ARM_CONTROL_R 0x0200
266 #define ARM_CONTROL_F 0x0400
267 #define ARM_CONTROL_Z 0x0800
268 #define ARM_CONTROL_ICACHE 0x1000
269 #define ARM_CONTROL_V 0x2000
270 #define ARM_CONTROL_RR 0x4000
271 #define ARM_CONTROL_L4 0x8000
274 #define ARM_AUXCTRL_MD 0x30
275 #define ARM_AUXCTRL_MD_SHIFT 4
276 #define ARM_AUXCTRL_P 0x02
277 #define ARM_AUXCTRL_K 0x01
280 #define ARM_CACHETYPE_CLASS 0x1e000000
281 #define ARM_CACHETYPE_CLASS_SHIFT 25
282 #define ARM_CACHETYPE_HARVARD 0x01000000
283 #define ARM_CACHETYPE_HARVARD_SHIFT 24
284 #define ARM_CACHETYPE_DSIZE 0x001c0000
285 #define ARM_CACHETYPE_DSIZE_SHIFT 18
286 #define ARM_CACHETYPE_DASSOC 0x00038000
287 #define ARM_CACHETYPE_DASSOC_SHIFT 15
288 #define ARM_CACHETYPE_DLINE 0x00003000
289 #define ARM_CACHETYPE_DLINE_SHIFT 12
290 #define ARM_CACHETYPE_ISIZE 0x000001c0
291 #define ARM_CACHETYPE_ISIZE_SHIFT 6
292 #define ARM_CACHETYPE_IASSOC 0x00000038
293 #define ARM_CACHETYPE_IASSOC_SHIFT 3
294 #define ARM_CACHETYPE_ILINE 0x00000003
295 #define ARM_CACHETYPE_ILINE_SHIFT 0
307 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
313 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
318 int crn,
int crm,
int rd);
320 int crn,
int crm,
int rd);
322 int crn,
int crm,
int rd);
325 void arm_push(
struct cpu*
cpu, uint32_t* np,
int p_bit,
int u_bit,
int s_bit,
int w_bit, uint16_t regs);
326 void arm_pop(
struct cpu*
cpu, uint32_t* np,
int p_bit,
int u_bit,
int s_bit,
int w_bit, uint32_t iw);
330 uint64_t *return_addr,
int flags);
332 uint64_t *return_addr,
int flags);
void arm_exception(struct cpu *, int)
int arm_cpu_family_init(struct cpu_family *)
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
int arm_cpu_interpret_thumb_SLOW(struct cpu *)
struct interrupt tmr1_irq
void arm_push(struct cpu *cpu, uint32_t *np, int p_bit, int u_bit, int s_bit, int w_bit, uint16_t regs)
#define VPH32_16BITVPHENTRIES(arch, ARCH)
uint32_t default_r8_r14[7]
void(* coproc[16])(struct cpu *, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
void arm_save_register_bank(struct cpu *cpu)
unsigned char * translation_table
void arm_load_register_bank(struct cpu *cpu)
#define DYNTRANS_ITC(arch)
struct interrupt tmr0_irq
#define VPH_TLBS(arch, ARCH)
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int arm_run_instr(struct cpu *cpu)
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
struct arm_cpu_type_def cpu_type
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
void arm_pop(struct cpu *cpu, uint32_t *np, int p_bit, int u_bit, int s_bit, int w_bit, uint32_t iw)
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
uint32_t is_userpage[N_VPH32_ENTRIES/32]
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
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