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Macros | |
#define | SH3_TRA 0xffffffd0 /* 32bit */ |
#define | SH3_EXPEVT 0xffffffd4 /* 32bit */ |
#define | SH3_INTEVT 0xffffffd8 /* 32bit */ |
#define | SH7709_INTEVT2 0xa4000000 /* 32bit */ |
#define | SH4_TRA 0xff000020 /* 32bit */ |
#define | SH4_EXPEVT 0xff000024 /* 32bit */ |
#define | SH4_INTEVT 0xff000028 /* 32bit */ |
#define | EXPEVT_RESET_POWER 0x000 /* Power-On reset */ |
#define | EXPEVT_RESET_MANUAL 0x020 /* Manual reset */ |
#define | EXPEVT_RESET_TLB_MULTI_HIT 0x140 /* SH4 only */ |
#define | EXPEVT_TLB_MISS_LD 0x040 /* TLB miss (load) */ |
#define | EXPEVT_TLB_MISS_ST 0x060 /* TLB miss (store) */ |
#define | EXPEVT_TLB_MOD 0x080 /* Initial page write */ |
#define | EXPEVT_TLB_PROT_LD 0x0a0 /* Protection violation (load) */ |
#define | EXPEVT_TLB_PROT_ST 0x0c0 /* Protection violation (store)*/ |
#define | EXPEVT_ADDR_ERR_LD 0x0e0 /* Address error (load) */ |
#define | EXPEVT_ADDR_ERR_ST 0x100 /* Address error (store) */ |
#define | EXPEVT_FPU 0x120 /* FPU exception */ |
#define | EXPEVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ |
#define | EXPEVT_RES_INST 0x180 /* Illegal instruction */ |
#define | EXPEVT_SLOT_INST 0x1a0 /* Illegal slot instruction */ |
#define | EXPEVT_BREAK 0x1e0 /* User break */ |
#define | EXPEVT_FPU_DISABLE 0x800 /* FPU disabled */ |
#define | EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */ |
#define | EXP_USER 0x001 /* exception from user-mode */ |
#define | _SH_TRA_BREAK 0xc3 /* magic number for debugger */ |
#define | SH_INTEVT_NMI 0x1c0 |
#define | SH_INTEVT_TMU0_TUNI0 0x400 |
#define | SH_INTEVT_TMU1_TUNI1 0x420 |
#define | SH_INTEVT_TMU2_TUNI2 0x440 |
#define | SH_INTEVT_TMU2_TICPI2 0x460 |
#define | SH_INTEVT_SCI_ERI 0x4e0 |
#define | SH_INTEVT_SCI_RXI 0x500 |
#define | SH_INTEVT_SCI_TXI 0x520 |
#define | SH_INTEVT_SCI_TEI 0x540 |
#define | SH_INTEVT_WDT_ITI 0x560 |
#define | SH_INTEVT_IRL9 0x320 |
#define | SH_INTEVT_IRL11 0x360 |
#define | SH_INTEVT_IRL13 0x3a0 |
#define | SH4_INTEVT_SCIF_ERI 0x700 |
#define | SH4_INTEVT_SCIF_RXI 0x720 |
#define | SH4_INTEVT_SCIF_BRI 0x740 |
#define | SH4_INTEVT_SCIF_TXI 0x760 |
#define | SH7709_INTEVT2_IRQ0 0x600 |
#define | SH7709_INTEVT2_IRQ1 0x620 |
#define | SH7709_INTEVT2_IRQ2 0x640 |
#define | SH7709_INTEVT2_IRQ3 0x660 |
#define | SH7709_INTEVT2_IRQ4 0x680 |
#define | SH7709_INTEVT2_IRQ5 0x6a0 |
#define | SH7709_INTEVT2_PINT07 0x700 |
#define | SH7709_INTEVT2_PINT8F 0x720 |
#define | SH7709_INTEVT2_DEI0 0x800 |
#define | SH7709_INTEVT2_DEI1 0x820 |
#define | SH7709_INTEVT2_DEI2 0x840 |
#define | SH7709_INTEVT2_DEI3 0x860 |
#define | SH7709_INTEVT2_IRDA_ERI 0x880 |
#define | SH7709_INTEVT2_IRDA_RXI 0x8a0 |
#define | SH7709_INTEVT2_IRDA_BRI 0x8c0 |
#define | SH7709_INTEVT2_IRDA_TXI 0x8e0 |
#define | SH7709_INTEVT2_SCIF_ERI 0x900 |
#define | SH7709_INTEVT2_SCIF_RXI 0x920 |
#define | SH7709_INTEVT2_SCIF_BRI 0x940 |
#define | SH7709_INTEVT2_SCIF_TXI 0x960 |
#define | SH7709_INTEVT2_ADC 0x980 |
#define | SH4_INTEVT_IRL0 0x240 |
#define | SH4_INTEVT_IRL1 0x2a0 |
#define | SH4_INTEVT_IRL2 0x300 |
#define | SH4_INTEVT_IRL3 0x360 |
#define | SH4_INTEVT_IRQ0 0x200 |
#define | SH4_INTEVT_IRQ1 0x220 |
#define | SH4_INTEVT_IRQ2 0x240 |
#define | SH4_INTEVT_IRQ3 0x260 |
#define | SH4_INTEVT_IRQ4 0x280 |
#define | SH4_INTEVT_IRQ5 0x2a0 |
#define | SH4_INTEVT_IRQ6 0x2c0 |
#define | SH4_INTEVT_IRQ7 0x2e0 |
#define | SH4_INTEVT_IRQ8 0x300 |
#define | SH4_INTEVT_IRQ9 0x320 |
#define | SH4_INTEVT_IRQ10 0x340 |
#define | SH4_INTEVT_IRQ11 0x360 |
#define | SH4_INTEVT_IRQ12 0x380 |
#define | SH4_INTEVT_IRQ13 0x3a0 |
#define | SH4_INTEVT_IRQ14 0x3c0 |
#define | SH4_INTEVT_IRQ15 0x3e0 |
#define | SH4_INTEVT_TMU3 0xb00 |
#define | SH4_INTEVT_TMU4 0xb80 |
#define | SH4_INTEVT_PCISERR 0xa00 |
#define | SH4_INTEVT_PCIERR 0xae0 |
#define | SH4_INTEVT_PCIPWDWN 0xac0 |
#define | SH4_INTEVT_PCIPWON 0xaa0 |
#define | SH4_INTEVT_PCIDMA0 0xa80 |
#define | SH4_INTEVT_PCIDMA1 0xa60 |
#define | SH4_INTEVT_PCIDMA2 0xa40 |
#define | SH4_INTEVT_PCIDMA3 0xa20 |
#define _SH_TRA_BREAK 0xc3 /* magic number for debugger */ |
Definition at line 81 of file sh4_exception.h.
#define EXP_USER 0x001 /* exception from user-mode */ |
Definition at line 79 of file sh4_exception.h.
#define EXPEVT_ADDR_ERR_LD 0x0e0 /* Address error (load) */ |
Definition at line 68 of file sh4_exception.h.
#define EXPEVT_ADDR_ERR_ST 0x100 /* Address error (store) */ |
Definition at line 69 of file sh4_exception.h.
#define EXPEVT_BREAK 0x1e0 /* User break */ |
Definition at line 74 of file sh4_exception.h.
#define EXPEVT_FPU 0x120 /* FPU exception */ |
Definition at line 70 of file sh4_exception.h.
#define EXPEVT_FPU_DISABLE 0x800 /* FPU disabled */ |
Definition at line 75 of file sh4_exception.h.
#define EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */ |
Definition at line 76 of file sh4_exception.h.
#define EXPEVT_RES_INST 0x180 /* Illegal instruction */ |
Definition at line 72 of file sh4_exception.h.
#define EXPEVT_RESET_MANUAL 0x020 /* Manual reset */ |
Definition at line 59 of file sh4_exception.h.
#define EXPEVT_RESET_POWER 0x000 /* Power-On reset */ |
Definition at line 58 of file sh4_exception.h.
#define EXPEVT_RESET_TLB_MULTI_HIT 0x140 /* SH4 only */ |
Definition at line 60 of file sh4_exception.h.
#define EXPEVT_SLOT_INST 0x1a0 /* Illegal slot instruction */ |
Definition at line 73 of file sh4_exception.h.
#define EXPEVT_TLB_MISS_LD 0x040 /* TLB miss (load) */ |
Definition at line 63 of file sh4_exception.h.
#define EXPEVT_TLB_MISS_ST 0x060 /* TLB miss (store) */ |
Definition at line 64 of file sh4_exception.h.
#define EXPEVT_TLB_MOD 0x080 /* Initial page write */ |
Definition at line 65 of file sh4_exception.h.
#define EXPEVT_TLB_PROT_LD 0x0a0 /* Protection violation (load) */ |
Definition at line 66 of file sh4_exception.h.
#define EXPEVT_TLB_PROT_ST 0x0c0 /* Protection violation (store)*/ |
Definition at line 67 of file sh4_exception.h.
#define EXPEVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ |
Definition at line 71 of file sh4_exception.h.
#define SH3_EXPEVT 0xffffffd4 /* 32bit */ |
Definition at line 46 of file sh4_exception.h.
#define SH3_INTEVT 0xffffffd8 /* 32bit */ |
Definition at line 47 of file sh4_exception.h.
#define SH3_TRA 0xffffffd0 /* 32bit */ |
Definition at line 45 of file sh4_exception.h.
#define SH4_EXPEVT 0xff000024 /* 32bit */ |
Definition at line 51 of file sh4_exception.h.
#define SH4_INTEVT 0xff000028 /* 32bit */ |
Definition at line 52 of file sh4_exception.h.
#define SH4_INTEVT_IRL0 0x240 |
Definition at line 138 of file sh4_exception.h.
#define SH4_INTEVT_IRL1 0x2a0 |
Definition at line 139 of file sh4_exception.h.
#define SH4_INTEVT_IRL2 0x300 |
Definition at line 140 of file sh4_exception.h.
#define SH4_INTEVT_IRL3 0x360 |
Definition at line 141 of file sh4_exception.h.
#define SH4_INTEVT_IRQ0 0x200 |
Definition at line 143 of file sh4_exception.h.
#define SH4_INTEVT_IRQ1 0x220 |
Definition at line 144 of file sh4_exception.h.
#define SH4_INTEVT_IRQ10 0x340 |
Definition at line 153 of file sh4_exception.h.
#define SH4_INTEVT_IRQ11 0x360 |
Definition at line 154 of file sh4_exception.h.
#define SH4_INTEVT_IRQ12 0x380 |
Definition at line 155 of file sh4_exception.h.
#define SH4_INTEVT_IRQ13 0x3a0 |
Definition at line 156 of file sh4_exception.h.
#define SH4_INTEVT_IRQ14 0x3c0 |
Definition at line 157 of file sh4_exception.h.
#define SH4_INTEVT_IRQ15 0x3e0 |
Definition at line 158 of file sh4_exception.h.
#define SH4_INTEVT_IRQ2 0x240 |
Definition at line 145 of file sh4_exception.h.
#define SH4_INTEVT_IRQ3 0x260 |
Definition at line 146 of file sh4_exception.h.
#define SH4_INTEVT_IRQ4 0x280 |
Definition at line 147 of file sh4_exception.h.
#define SH4_INTEVT_IRQ5 0x2a0 |
Definition at line 148 of file sh4_exception.h.
#define SH4_INTEVT_IRQ6 0x2c0 |
Definition at line 149 of file sh4_exception.h.
#define SH4_INTEVT_IRQ7 0x2e0 |
Definition at line 150 of file sh4_exception.h.
#define SH4_INTEVT_IRQ8 0x300 |
Definition at line 151 of file sh4_exception.h.
#define SH4_INTEVT_IRQ9 0x320 |
Definition at line 152 of file sh4_exception.h.
#define SH4_INTEVT_PCIDMA0 0xa80 |
Definition at line 167 of file sh4_exception.h.
#define SH4_INTEVT_PCIDMA1 0xa60 |
Definition at line 168 of file sh4_exception.h.
#define SH4_INTEVT_PCIDMA2 0xa40 |
Definition at line 169 of file sh4_exception.h.
#define SH4_INTEVT_PCIDMA3 0xa20 |
Definition at line 170 of file sh4_exception.h.
#define SH4_INTEVT_PCIERR 0xae0 |
Definition at line 164 of file sh4_exception.h.
#define SH4_INTEVT_PCIPWDWN 0xac0 |
Definition at line 165 of file sh4_exception.h.
#define SH4_INTEVT_PCIPWON 0xaa0 |
Definition at line 166 of file sh4_exception.h.
#define SH4_INTEVT_PCISERR 0xa00 |
Definition at line 163 of file sh4_exception.h.
#define SH4_INTEVT_SCIF_BRI 0x740 |
Definition at line 107 of file sh4_exception.h.
#define SH4_INTEVT_SCIF_ERI 0x700 |
Definition at line 105 of file sh4_exception.h.
#define SH4_INTEVT_SCIF_RXI 0x720 |
Definition at line 106 of file sh4_exception.h.
#define SH4_INTEVT_SCIF_TXI 0x760 |
Definition at line 108 of file sh4_exception.h.
#define SH4_INTEVT_TMU3 0xb00 |
Definition at line 160 of file sh4_exception.h.
#define SH4_INTEVT_TMU4 0xb80 |
Definition at line 161 of file sh4_exception.h.
#define SH4_TRA 0xff000020 /* 32bit */ |
Definition at line 50 of file sh4_exception.h.
#define SH7709_INTEVT2 0xa4000000 /* 32bit */ |
Definition at line 48 of file sh4_exception.h.
#define SH7709_INTEVT2_ADC 0x980 |
Definition at line 135 of file sh4_exception.h.
#define SH7709_INTEVT2_DEI0 0x800 |
Definition at line 120 of file sh4_exception.h.
#define SH7709_INTEVT2_DEI1 0x820 |
Definition at line 121 of file sh4_exception.h.
#define SH7709_INTEVT2_DEI2 0x840 |
Definition at line 122 of file sh4_exception.h.
#define SH7709_INTEVT2_DEI3 0x860 |
Definition at line 123 of file sh4_exception.h.
#define SH7709_INTEVT2_IRDA_BRI 0x8c0 |
Definition at line 127 of file sh4_exception.h.
#define SH7709_INTEVT2_IRDA_ERI 0x880 |
Definition at line 125 of file sh4_exception.h.
#define SH7709_INTEVT2_IRDA_RXI 0x8a0 |
Definition at line 126 of file sh4_exception.h.
#define SH7709_INTEVT2_IRDA_TXI 0x8e0 |
Definition at line 128 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ0 0x600 |
Definition at line 110 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ1 0x620 |
Definition at line 111 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ2 0x640 |
Definition at line 112 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ3 0x660 |
Definition at line 113 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ4 0x680 |
Definition at line 114 of file sh4_exception.h.
#define SH7709_INTEVT2_IRQ5 0x6a0 |
Definition at line 115 of file sh4_exception.h.
#define SH7709_INTEVT2_PINT07 0x700 |
Definition at line 117 of file sh4_exception.h.
#define SH7709_INTEVT2_PINT8F 0x720 |
Definition at line 118 of file sh4_exception.h.
#define SH7709_INTEVT2_SCIF_BRI 0x940 |
Definition at line 132 of file sh4_exception.h.
#define SH7709_INTEVT2_SCIF_ERI 0x900 |
Definition at line 130 of file sh4_exception.h.
#define SH7709_INTEVT2_SCIF_RXI 0x920 |
Definition at line 131 of file sh4_exception.h.
#define SH7709_INTEVT2_SCIF_TXI 0x960 |
Definition at line 133 of file sh4_exception.h.
#define SH_INTEVT_IRL11 0x360 |
Definition at line 102 of file sh4_exception.h.
#define SH_INTEVT_IRL13 0x3a0 |
Definition at line 103 of file sh4_exception.h.
#define SH_INTEVT_IRL9 0x320 |
Definition at line 101 of file sh4_exception.h.
#define SH_INTEVT_NMI 0x1c0 |
Definition at line 87 of file sh4_exception.h.
#define SH_INTEVT_SCI_ERI 0x4e0 |
Definition at line 94 of file sh4_exception.h.
#define SH_INTEVT_SCI_RXI 0x500 |
Definition at line 95 of file sh4_exception.h.
#define SH_INTEVT_SCI_TEI 0x540 |
Definition at line 97 of file sh4_exception.h.
#define SH_INTEVT_SCI_TXI 0x520 |
Definition at line 96 of file sh4_exception.h.
#define SH_INTEVT_TMU0_TUNI0 0x400 |
Definition at line 89 of file sh4_exception.h.
#define SH_INTEVT_TMU1_TUNI1 0x420 |
Definition at line 90 of file sh4_exception.h.
#define SH_INTEVT_TMU2_TICPI2 0x460 |
Definition at line 92 of file sh4_exception.h.
#define SH_INTEVT_TMU2_TUNI2 0x440 |
Definition at line 91 of file sh4_exception.h.
#define SH_INTEVT_WDT_ITI 0x560 |
Definition at line 99 of file sh4_exception.h.