#include "ns16550reg.h"
Go to the source code of this file.
Macros | |
#define | COM_FREQ 1843200 /* 16-bit baud rate divisor */ |
#define | COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ |
#define | IER_ERXRDY 0x1 /* Enable receiver interrupt */ |
#define | IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */ |
#define | IER_ERLS 0x4 /* Enable line status interrupt */ |
#define | IER_EMSC 0x8 /* Enable modem status interrupt */ |
#define | IER_ERTS 0x40 /* Enable RTS interrupt */ |
#define | IER_ECTS 0x80 /* Enable CTS interrupt */ |
#define | IIR_IMASK 0xf |
#define | IIR_RXTOUT 0xc |
#define | IIR_RLS 0x6 /* Line status change */ |
#define | IIR_RXRDY 0x4 /* Receiver ready */ |
#define | IIR_TXRDY 0x2 /* Transmitter ready */ |
#define | IIR_MLSC 0x0 /* Modem status */ |
#define | IIR_NOPEND 0x1 /* No pending interrupts */ |
#define | IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ |
#define | FIFO_ENABLE 0x01 /* Turn the FIFO on */ |
#define | FIFO_RCV_RST 0x02 /* Reset RX FIFO */ |
#define | FIFO_XMT_RST 0x04 /* Reset TX FIFO */ |
#define | FIFO_DMA_MODE 0x08 |
#define | FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */ |
#define | FIFO_TRIGGER_4 0x40 /* ibid 4 */ |
#define | FIFO_TRIGGER_8 0x80 /* ibid 8 */ |
#define | FIFO_TRIGGER_14 0xc0 /* ibid 14 */ |
#define | EFR_AUTOCTS 0x80 /* Automatic CTS flow control */ |
#define | EFR_AUTORTS 0x40 /* Automatic RTS flow control */ |
#define | EFR_SPECIAL 0x20 /* Special char detect */ |
#define | EFR_EFCR 0x10 /* Enhanced function control bit */ |
#define | EFR_TXFLOWBOTH 0x0c /* Automatic transmit XON/XOFF 1 and 2 */ |
#define | EFR_TXFLOW1 0x08 /* Automatic transmit XON/XOFF 1 */ |
#define | EFR_TXFLOW2 0x04 /* Automatic transmit XON/XOFF 2 */ |
#define | EFR_TXFLOWNONE 0x00 /* No automatic XON/XOFF transmit */ |
#define | EFR_RXFLOWBOTH 0x03 /* Automatic receive XON/XOFF 1 and 2 */ |
#define | EFR_RXFLOW1 0x02 /* Automatic receive XON/XOFF 1 */ |
#define | EFR_RXFLOW2 0x01 /* Automatic receive XON/XOFF 2 */ |
#define | EFR_RXFLOWNONE 0x00 /* No automatic XON/XOFF receive */ |
#define | LCR_EERS 0xBF /* Enable access to Enhanced Register Set */ |
#define | LCR_DLAB 0x80 /* Divisor latch access enable */ |
#define | LCR_SBREAK 0x40 /* Break Control */ |
#define | LCR_PZERO 0x38 /* Space parity */ |
#define | LCR_PONE 0x28 /* Mark parity */ |
#define | LCR_PEVEN 0x18 /* Even parity */ |
#define | LCR_PODD 0x08 /* Odd parity */ |
#define | LCR_PNONE 0x00 /* No parity */ |
#define | LCR_PENAB 0x08 /* XXX - low order bit of all parity */ |
#define | LCR_STOPB 0x04 /* 2 stop bits per serial word */ |
#define | LCR_8BITS 0x03 /* 8 bits per serial word */ |
#define | LCR_7BITS 0x02 /* 7 bits */ |
#define | LCR_6BITS 0x01 /* 6 bits */ |
#define | LCR_5BITS 0x00 /* 5 bits */ |
#define | MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */ |
#define | MCR_IENABLE 0x08 /* Out2: enables UART interrupts */ |
#define | MCR_DRS 0x04 /* Out1: resets some internal modems */ |
#define | MCR_RTS 0x02 /* Request To Send */ |
#define | MCR_DTR 0x01 /* Data Terminal Ready */ |
#define | LSR_RCV_FIFO 0x80 |
#define | LSR_TSRE 0x40 /* Transmitter empty: byte sent */ |
#define | LSR_TXRDY 0x20 /* Transmitter buffer empty */ |
#define | LSR_BI 0x10 /* Break detected */ |
#define | LSR_FE 0x08 /* Framing error: bad stop bit */ |
#define | LSR_PE 0x04 /* Parity error */ |
#define | LSR_OE 0x02 /* Overrun, lost incoming byte */ |
#define | LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */ |
#define | LSR_RCV_MASK 0x1f /* Mask for incoming data or error */ |
#define | MSR_DCD 0x80 /* Current Data Carrier Detect */ |
#define | MSR_RI 0x40 /* Current Ring Indicator */ |
#define | MSR_DSR 0x20 /* Current Data Set Ready */ |
#define | MSR_CTS 0x10 /* Current Clear to Send */ |
#define | MSR_DDCD 0x08 /* DCD has changed state */ |
#define | MSR_TERI 0x04 /* RI has toggled low to high */ |
#define | MSR_DDSR 0x02 /* DSR has changed state */ |
#define | MSR_DCTS 0x01 /* CTS has changed state */ |
#define | COM_NPORTS 8 |
#define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ |
#define EFR_RXFLOWBOTH 0x03 /* Automatic receive XON/XOFF 1 and 2 */ |
#define EFR_RXFLOWNONE 0x00 /* No automatic XON/XOFF receive */ |
#define EFR_TXFLOW1 0x08 /* Automatic transmit XON/XOFF 1 */ |
#define EFR_TXFLOW2 0x04 /* Automatic transmit XON/XOFF 2 */ |
#define EFR_TXFLOWBOTH 0x0c /* Automatic transmit XON/XOFF 1 and 2 */ |
#define EFR_TXFLOWNONE 0x00 /* No automatic XON/XOFF transmit */ |
#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */ |
#define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */ |
#define LCR_EERS 0xBF /* Enable access to Enhanced Register Set */ |
#define LCR_PENAB 0x08 /* XXX - low order bit of all parity */ |
#define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */ |
#define MCR_DRS 0x04 /* Out1: resets some internal modems */ |
#define MCR_IENABLE 0x08 /* Out2: enables UART interrupts */ |
#define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */ |