cpu_m88k.cc Source File
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58 #define DYNTRANS_DELAYSLOT
65 static const char *memop[4] = {
".d",
"",
".h",
".b" };
74 static const char *m88k_cr_name(
struct cpu *
cpu,
int i)
76 const char **cr_names = m88k_cr_names;
80 cr_names = m88k_cr_197_names;
85 static char *m88k_fcr_name(
struct cpu *
cpu,
int fi)
88 static char fcr_name[10];
89 snprintf(fcr_name,
sizeof(fcr_name),
"FCR%i", fi);
109 while (i >= 0 && cpu_type_defs[i].
name != NULL) {
110 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
148 snprintf(
name,
sizeof(
name),
"r%i", i);
154 snprintf(
name,
sizeof(
name),
"%s", m88k_cr_name(
cpu, i));
160 snprintf(
name,
sizeof(
name),
"%s", m88k_fcr_name(
cpu, i));
171 memset(&templ, 0,
sizeof(templ));
220 while (tdefs[i].
name != NULL) {
225 if ((i % 5) == 0 || tdefs[i].
name == NULL)
238 uint32_t iword = *((uint32_t *)&ib[0]);
245 switch (iword >> 26) {
253 switch ((iword >> 8) & 0xff) {
281 debug(
"cpu%i: pc = 0x%08" PRIx32, x, (uint32_t)
cpu->
pc);
290 debug(
" r%-2i = 0x%08" PRIx32,
298 int n_control_regs = 32;
304 for (i=0; i<n_control_regs; i++) {
307 debug(
" %4s=0x%08" PRIx32,
315 int n_fpu_control_regs = 64;
317 for (i=0; i<n_fpu_control_regs; i++) {
320 debug(
" %5s=0x%08" PRIx32,
340 int cpu_nr, cmmu_nr, i;
342 for (cpu_nr = 0; cpu_nr < m->
ncpus; cpu_nr++) {
345 if (x != -1 && cpu_nr != x)
353 printf(
"cpu%i: CMMU %i (%s)\n", cpu_nr, cmmu_nr,
354 cmmu_nr & 1?
"data" :
"instruction");
358 uint32_t b = cmmu->
batc[i];
359 printf(
"cpu%i: BATC[%2i]: ", cpu_nr, i);
360 printf(
"v=0x%08" PRIx32, b & 0xfff80000);
361 printf(
", p=0x%08" PRIx32,
362 (b << 13) & 0xfff80000);
363 printf(
", %s %s %s %s %s %s\n",
377 printf(
"cpu%i: patc[%2i]: ", cpu_nr, i);
382 printf(
" v=0x%08" PRIx32, v & 0xfffff000);
383 printf(
", p=0x%08" PRIx32, p & 0xfffff000);
385 printf(
" %s %s %s %s %s %s %s",
386 v &
PG_U1?
"U1 " :
"!u1",
387 v &
PG_U0?
"U0 " :
"!u0",
388 v &
PG_SO?
"SP " :
"!sp",
389 v &
PG_M?
"M " :
"!m",
390 v &
PG_U?
"U " :
"!u",
392 v &
PG_V?
"V " :
"!v");
461 fatal(
"DMT DREG = zero? Internal error.\n");
467 fatal(
"DMT byte order not same as CPUs?\n");
482 fatal(
"DMAx not word-aligned? Internal error.\n");
488 default:
fatal(
"m88k_ldcr: UNIMPLEMENTED cr = 0x%02x (%s)\n",
489 cr, m88k_cr_name(
cpu, cr));
514 fatal(
"TODO: attempt to change endianness by flipping"
515 " the endianness bit in the PSR. How should this"
516 " be handled? Aborting.\n");
521 fatal(
"[ m88k_stcr: WARNING! the PSR_MODE bit is being"
522 " cleared; this should be done using the RTE "
523 "instruction only, according to the M88100 "
524 "manual! Continuing anyway. ]\n");
527 fatal(
"m88k_stcr: TODO: MXM support\n");
550 fatal(
"[ m88k_stcr: WARNING! bit 0 non-zero when"
551 " writing to SSBR (?) ]\n");
556 if (value & 0x00000fff)
557 fatal(
"[ m88k_stcr: WARNING! bits 0..11 non-zero when"
558 " writing to VBR (?) ]\n");
575 default:
fatal(
"m88k_stcr: UNIMPLEMENTED cr = 0x%02x (%s)\n",
576 cr, m88k_cr_name(
cpu, cr));
594 default:
fatal(
"m88k_fstcr: UNIMPLEMENTED fcr = 0x%02x (%s)\n",
595 fcr, m88k_fcr_name(
cpu, fcr));
609 static void m88k_memory_transaction_debug_dump(
struct cpu *
cpu,
int n)
613 debug(
"[ DMT%i: ", n);
616 debug(
"Little-Endian, ");
618 debug(
"Big-Endian, ");
620 debug(
"Supervisor, ");
630 debug(
"load.%c(r%i), ",
639 debug(
"not valid ]\n");
650 int update_shadow_regs = 1;
652 debug(
"[ EXCEPTION 0x%03x: ", vector);
655 debug(
"RESET");
break;
657 debug(
"INTERRUPT");
break;
659 debug(
"INSTRUCTION_ACCESS");
break;
661 debug(
"DATA_ACCESS");
break;
663 debug(
"MISALIGNED_ACCESS");
break;
665 debug(
"UNIMPLEMENTED_OPCODE");
break;
667 debug(
"PRIVILEGE_VIOLATION");
break;
669 debug(
"BOUNDS_CHECK_VIOLATION");
break;
671 debug(
"ILLEGAL_INTEGER_DIVIDE");
break;
673 debug(
"INTEGER_OVERFLOW");
break;
675 debug(
"ERROR");
break;
677 debug(
"SFU1_PRECISE");
break;
679 debug(
"SFU1_IMPRECISE");
break;
689 debug(
"MVMEPROM_VECTOR");
break;
690 default:
debug(
"unknown");
break;
702 fatal(
"[ SFRZ already set in PSR => ERROR ]\n");
705 update_shadow_regs = 0;
718 if (update_shadow_regs) {
770 fatal(
"[ m88k_exception: reset ]\n");
801 m88k_memory_transaction_debug_dump(
cpu, 0);
802 m88k_memory_transaction_debug_dump(
cpu, 1);
813 default:
fatal(
"m88k_exception(): 0x%x: TODO\n", vector);
836 int running, uint64_t dumpaddr)
840 const char *
symbol, *mnem = NULL;
842 uint32_t op26, op10, op11, d, s1, s2, w5, cr6, imm16;
850 if (
symbol != NULL && offset == 0 && supervisor)
856 debug(
"%c%08" PRIx32
": ",
858 (uint32_t) dumpaddr);
861 iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
863 iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
865 debug(
"%08" PRIx32, (uint32_t) iw);
872 op26 = (iw >> 26) & 0x3f;
873 op11 = (iw >> 11) & 0x1f;
874 op10 = (iw >> 10) & 0x3f;
875 d = (iw >> 21) & 0x1f;
876 s1 = (iw >> 16) & 0x1f;
879 w5 = (iw >> 5) & 0x1f;
880 cr6 = (iw >> 5) & 0x3f;
881 d16 = ((int16_t) (iw & 0xffff)) * 4;
882 d26 = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4;
898 if (iw == 0x00000000) {
903 case 0x00:
debug(
"xmem.bu");
break;
904 case 0x01:
debug(
"xmem");
break;
905 case 0x02:
debug(
"ld.hu");
break;
906 case 0x03:
debug(
"ld.bu");
break;
907 default:
debug(
"%s%s", op26 >= 0x08?
"st" :
"ld",
910 debug(
"\tr%i,r%i,0x%x", d, s1, imm16);
912 uint32_t tmpaddr =
cpu->
cd.
m88k.
r[s1] + imm16;
915 if (
symbol != NULL && supervisor)
918 debug(
"\t; [0x%08" PRIx32
"]", tmpaddr);
923 case 0:
debug(
"0x%016" PRIx64, (uint64_t)
928 case 1:
debug(
"0x%08" PRIx32,
931 case 2:
debug(
"0x%04" PRIx16,
934 case 3:
debug(
"0x%02" PRIx8,
955 dumpaddr -
sizeof(uint32_t), (
unsigned char *)&iw2,
962 if ((iw2 >> 26) == 0x17 &&
963 ((iw2 >> 21) & 0x1f) == s1) {
964 uint32_t tmpaddr = (iw2 << 16) + imm16;
968 if (
symbol != NULL && supervisor)
971 debug(
"\t; [0x%08" PRIx32
"]", tmpaddr);
990 case 0x11: mnem =
"and";
break;
992 case 0x13: mnem =
"mask";
break;
994 case 0x15: mnem =
"xor";
break;
996 case 0x17: mnem =
"or";
break;
1001 debug(
"\t\t; weird nop encoding: ");
1002 debug(
"%s%s\t", mnem, op26 & 1?
".u" :
"");
1003 debug(
"r%i,r%i,0x%x", d, s1, imm16);
1018 dumpaddr -
sizeof(uint32_t), (
unsigned char *)&iw2,
1025 if ((iw2 >> 26) == 0x17 &&
1026 ((iw2 >> 21) & 0x1f) == s1) {
1027 uint32_t tmpaddr = (iw2 << 16) + imm16;
1032 if (
symbol != NULL && supervisor)
1035 debug(
"0x%08" PRIx32, tmpaddr);
1051 case 0x18: mnem =
"addu";
break;
1052 case 0x19: mnem =
"subu";
break;
1053 case 0x1a: mnem =
"divu";
break;
1054 case 0x1b: mnem =
"mulu";
break;
1055 case 0x1c: mnem =
"add";
break;
1056 case 0x1d: mnem =
"sub";
break;
1057 case 0x1e: mnem =
"div";
break;
1058 case 0x1f: mnem =
"cmp";
break;
1060 debug(
"%s\tr%i,r%i,%i\n", mnem, d, s1, imm16);
1064 if ((iw & 0x001ff81f) == 0x00004000) {
1065 debug(
"ldcr\tr%i,%s", d, m88k_cr_name(
cpu, cr6));
1069 }
else if ((iw & 0x001ff81f) == 0x00004800) {
1070 debug(
"fldcr\tr%i,%s\n", d, m88k_fcr_name(
cpu, cr6));
1071 }
else if ((iw & 0x03e0f800) == 0x00008000) {
1072 debug(
"stcr\tr%i,%s", s1, m88k_cr_name(
cpu, cr6));
1074 debug(
"\t\t; NOTE: weird encoding: "
1075 "low 5 bits = 0x%02x", s2);
1079 }
else if ((iw & 0x03e0f800) == 0x00008800) {
1080 debug(
"fstcr\tr%i,%s", s1,
1081 m88k_fcr_name(
cpu, cr6));
1083 debug(
"\t\t; NOTE: weird encoding: "
1084 "low 5 bits = 0x%02x", s2);
1086 }
else if ((iw & 0x0000f800) == 0x0000c000) {
1087 debug(
"xcr\tr%i,r%i,%s", d, s1,
1088 m88k_cr_name(
cpu, cr6));
1090 debug(
"\t\t; NOTE: weird encoding: "
1091 "low 5 bits = 0x%02x", s2);
1093 }
else if ((iw & 0x0000f800) == 0x0000c800) {
1094 debug(
"fxcr\tr%i,r%i,%s", d, s1,
1095 m88k_fcr_name(
cpu, cr6));
1097 debug(
"\t\t; NOTE: weird encoding: "
1098 "low 5 bits = 0x%02x", s2);
1101 debug(
"UNIMPLEMENTED 0x20\n");
1113 case 0x00: mnem =
"fmul";
break;
1114 case 0x05: mnem =
"fadd";
break;
1115 case 0x06: mnem =
"fsub";
break;
1116 case 0x07: mnem =
"fcmp";
break;
1117 case 0x0e: mnem =
"fdiv";
break;
1119 debug(
"%s.%c%c%c r%i,r%i,r%i\n",
1121 ((iw >> 5) & 1)?
'd' :
's',
1122 ((iw >> 9) & 1)?
'd' :
's',
1123 ((iw >> 7) & 1)?
'd' :
's',
1128 case 0x04: mnem =
"flt";
break;
1130 debug(
"%s.%cs\tr%i,r%i\n",
1132 ((iw >> 5) & 1)?
'd' :
's',
1139 case 0x09: mnem =
"int";
break;
1140 case 0x0a: mnem =
"nint";
break;
1141 case 0x0b: mnem =
"trnc";
break;
1143 debug(
"%s.s%c r%i,r%i\n",
1145 ((iw >> 7) & 1)?
'd' :
's',
1148 default:
debug(
"UNIMPLEMENTED 0x21, op11=0x%02x\n", op11);
1157 op26 >= 0x32?
"s" :
"",
1158 op26 & 1?
".n" :
"");
1159 debug(
"0x%08" PRIx32, (uint32_t) (dumpaddr + d26));
1161 dumpaddr + d26, &offset);
1162 if (
symbol != NULL && supervisor)
1175 case 0x35: mnem =
"bb0";
break;
1177 case 0x37: mnem =
"bb1";
break;
1179 case 0x3b: mnem =
"bcnd";
break;
1181 debug(
"%s%s\t", mnem, op26 & 1?
".n" :
"");
1182 if (op26 == 0x3a || op26 == 0x3b) {
1185 case 0x1:
debug(
"gt0");
break;
1186 case 0x2:
debug(
"eq0");
break;
1187 case 0x3:
debug(
"ge0");
break;
1188 case 0x7:
debug(
"not_maxneg");
break;
1189 case 0x8:
debug(
"maxneg");
break;
1190 case 0xc:
debug(
"lt0");
break;
1191 case 0xd:
debug(
"ne0");
break;
1192 case 0xe:
debug(
"le0");
break;
1193 default:
debug(
"unimplemented_%i", d);
1198 debug(
",r%i,0x%08" PRIx32, s1, (uint32_t) (dumpaddr + d16));
1200 dumpaddr + d16, &offset);
1201 if (
symbol != NULL && supervisor)
1207 if ((iw & 0x0000f000)==0x1000 || (iw & 0x0000f000)==0x2000) {
1211 debug(
"%s", (iw & 0x0000f000) == 0x1000?
"ld" :
"st");
1212 switch (iw & 0x00000c00) {
1213 case 0x000: scale = 8;
debug(
".d");
break;
1214 case 0x400: scale = 4;
break;
1215 case 0x800:
debug(
".x");
break;
1216 default:
debug(
".UNIMPLEMENTED");
1222 debug(
"\tr%i,r%i", d, s1);
1236 if (
symbol != NULL && supervisor)
1239 debug(
"\t; [0x%08" PRIx32
"]", tmpaddr);
1243 }
else switch (op10) {
1251 case 0x20: mnem =
"clr";
break;
1252 case 0x22: mnem =
"set";
break;
1253 case 0x24: mnem =
"ext";
break;
1254 case 0x26: mnem =
"extu";
break;
1255 case 0x28: mnem =
"mak";
break;
1256 case 0x2a: mnem =
"rot";
break;
1258 debug(
"%s\tr%i,r%i,", mnem, d, s1);
1263 debug(
"<%i>\n", s2);
1268 case 0x34: mnem =
"tb0";
break;
1269 case 0x36: mnem =
"tb1";
break;
1271 debug(
"%s\t%i,r%i,0x%x\n", mnem, d, s1, iw & 0x1ff);
1273 default:
debug(
"UNIMPLEMENTED 0x3c, op10=0x%02x\n", op10);
1278 if ((iw & 0xf000) <= 0x3fff) {
1282 switch (iw & 0xf000) {
1283 case 0x2000:
debug(
"st");
break;
1284 case 0x3000:
debug(
"lda");
break;
1285 default:
if ((iw & 0xf800) >= 0x0800)
1290 if ((iw & 0xf000) >= 0x1000) {
1292 scale = 1 << (3 - ((iw >> 10) & 3));
1293 debug(
"%s", memop[(iw >> 10) & 3]);
1294 }
else if ((iw & 0xf800) == 0x0000) {
1299 debug(
".bu"), scale = 1;
1302 if ((iw & 0xf00) < 0xc00)
1303 debug(
".hu"), scale = 2;
1305 debug(
".bu"), scale = 1;
1311 debug(
"\tr%i,r%i", d, s1);
1325 if (
symbol != NULL && supervisor)
1328 debug(
"\t; [0x%08" PRIx32
"]", tmpaddr);
1332 }
else switch ((iw >> 8) & 0xff) {
1369 switch ((iw >> 8) & 0xff) {
1370 case 0x40: mnem =
"and";
break;
1371 case 0x44: mnem =
"and.c";
break;
1372 case 0x50: mnem =
"xor";
break;
1373 case 0x54: mnem =
"xor.c";
break;
1374 case 0x58: mnem =
"or";
break;
1375 case 0x5c: mnem =
"or.c";
break;
1376 case 0x60: mnem =
"addu";
break;
1377 case 0x61: mnem =
"addu.co";
break;
1378 case 0x62: mnem =
"addu.ci";
break;
1379 case 0x63: mnem =
"addu.cio";
break;
1380 case 0x64: mnem =
"subu";
break;
1381 case 0x65: mnem =
"subu.co";
break;
1382 case 0x66: mnem =
"subu.ci";
break;
1383 case 0x67: mnem =
"subu.cio";
break;
1384 case 0x68: mnem =
"divu";
break;
1385 case 0x69: mnem =
"divu.d";
break;
1386 case 0x6c: mnem =
"mul";
break;
1387 case 0x6d: mnem =
"mulu.d";
break;
1388 case 0x6e: mnem =
"muls";
break;
1389 case 0x70: mnem =
"add";
break;
1390 case 0x71: mnem =
"add.co";
break;
1391 case 0x72: mnem =
"add.ci";
break;
1392 case 0x73: mnem =
"add.cio";
break;
1393 case 0x74: mnem =
"sub";
break;
1394 case 0x75: mnem =
"sub.co";
break;
1395 case 0x76: mnem =
"sub.ci";
break;
1396 case 0x77: mnem =
"sub.cio";
break;
1397 case 0x78: mnem =
"div";
break;
1398 case 0x7c: mnem =
"cmp";
break;
1399 case 0x80: mnem =
"clr";
break;
1400 case 0x88: mnem =
"set";
break;
1401 case 0x90: mnem =
"ext";
break;
1402 case 0x98: mnem =
"extu";
break;
1403 case 0xa0: mnem =
"mak";
break;
1404 case 0xa8: mnem =
"rot";
break;
1412 debug(
"\t\t; weird nop encoding: ");
1413 debug(
"%s\tr%i,r%i,r%i", mnem, d, s1, s2);
1422 debug(
"%s%s\t(r%i)",
1423 op11 & 1?
"jsr" :
"jmp",
1424 iw & 0x400?
".n" :
"",
1431 if (
symbol != NULL && supervisor)
1434 debug(
"0x%08" PRIx32, tmpaddr);
1440 debug(
"%s\tr%i,r%i\n",
1441 ((iw >> 8) & 0xff) == 0xe8 ?
"ff1" :
"ff0", d, s2);
1444 debug(
"tbnd\tr%i,r%i\n", s1, s2);
1447 switch (iw & 0xff) {
1454 debug(
"illop%i\n", iw & 0xff);
1457 debug(
"gxemul_prom_call\n");
1459 default:
debug(
"UNIMPLEMENTED 0x3d,0xfc: 0x%02x\n",
1463 default:
debug(
"UNIMPLEMENTED 0x3d, opbyte = 0x%02x\n",
1469 debug(
"tbnd\tr%i,0x%x\n", s1, imm16);
1472 default:
debug(
"UNIMPLEMENTED op26=0x%02x\n", op26);
1475 return sizeof(uint32_t);
#define M8820X_PATC_SUPERVISOR_BIT
struct m8820x_cmmu * cmmu[MAX_M8820X_CMMUS]
#define M88K_EXCEPTION_INTEGER_OVERFLOW
void m88k_irq_interrupt_deassert(struct interrupt *interrupt)
struct m88k_cpu_type_def cpu_type
#define M88K_EXCEPTION_PRIVILEGE_VIOLATION
void m88k_cpu_list_available_types(void)
int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
int m88k_run_instr(struct cpu *cpu)
#define M88K_CR_NAMES_197
void(* interrupt_deassert)(struct interrupt *)
struct symbol_context symbol_context
#define CPU_SETTINGS_ADD_REGISTER32(name, var)
#define M88K_EXCEPTION_INSTRUCTION_ACCESS
void m88k_cpu_functioncall_trace(struct cpu *cpu, int n_args)
#define N_M88200_BATC_REGS
#define N_M88K_FPU_CONTROL_REGS
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
#define N_M88200_PATC_ENTRIES
#define M88K_EXCEPTION_DATA_ACCESS
int(* instruction_has_delayslot)(struct cpu *cpu, unsigned char *ib)
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
int m88k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, int running, uint64_t dumpaddr)
void m88k_irq_interrupt_assert(struct interrupt *interrupt)
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
uint32_t patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES]
void m88k_cpu_dumpinfo(struct cpu *cpu)
#define M88K_CPU_TYPE_DEFS
void m88k_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void m88k_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void m88k_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
void fatal(const char *fmt,...)
int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
#define CACHE_INSTRUCTION
void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte)
#define M88K_EXCEPTION_ERROR
#define M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE
#define M88K_EXCEPTION_USER_TRAPS_START
uint32_t patc_v_and_control[N_M88200_PATC_ENTRIES]
void m88k_exception(struct cpu *cpu, int vector, int is_trap)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
void m88k_pc_to_pointers(struct cpu *)
uint32_t cr[N_M88K_CONTROL_REGS]
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
uint32_t physical_ram_in_mb
#define EMUL_LITTLE_ENDIAN
#define M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION
void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr)
#define M88K_EXCEPTION_SFU1_PRECISE
void m88k_cpu_tlbdump(struct machine *m, int x, int rawflag)
void m88k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
int m88k_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
#define M88K_EXCEPTION_RESET
int(* run_instr)(struct cpu *cpu)
int m88k_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
#define N_M88K_CONTROL_REGS
void(* interrupt_assert)(struct interrupt *)
uint32_t r[N_M88K_REGS+1]
void interrupt_handler_register(struct interrupt *templ)
#define M88K_EXCEPTION_UNIMPLEMENTED_OPCODE
#define M88K_EXCEPTION_MISALIGNED_ACCESS
#define M88K_EXCEPTION_SFU1_IMPRECISE
uint32_t batc[N_M88200_BATC_REGS]
uint32_t fcr[N_M88K_FPU_CONTROL_REGS]
#define EXCEPTION_IN_DELAY_SLOT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
#define MACHINE_MVME88K_197
#define M88K_EXCEPTION_INTERRUPT
void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr)
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