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Macros | |
#define | wd_data 0 /* data register (R/W - 16 bits) */ |
#define | wd_error 1 /* error register (R) */ |
#define | wd_precomp 1 /* write precompensation (W) */ |
#define | wd_features 1 /* features (W), same as wd_precomp */ |
#define | wd_seccnt 2 /* sector count (R/W) */ |
#define | wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ |
#define | wd_sector 3 /* first sector number (R/W) */ |
#define | wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ |
#define | wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ |
#define | wd_sdh 6 /* sector size/drive/head (R/W) */ |
#define | wd_command 7 /* command register (W) */ |
#define | wd_status 7 /* immediate status (R) */ |
#define | wd_lba_lo 3 /* lba address, low byte (RW) */ |
#define | wd_lba_mi 4 /* lba address, middle byte (RW) */ |
#define | wd_lba_hi 5 /* lba address, high byte (RW) */ |
#define | wd_aux_altsts 0 /* alternate fixed disk status (R) */ |
#define | wd_aux_ctlr 0 /* fixed disk controller control (W) */ |
#define | WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ |
#define | WDCTL_RST 0x04 /* reset the controller */ |
#define | WDCTL_IDS 0x02 /* disable controller interrupts */ |
#define | WDCS_BSY 0x80 /* busy */ |
#define | WDCS_DRDY 0x40 /* drive ready */ |
#define | WDCS_DWF 0x20 /* drive write fault */ |
#define | WDCS_DSC 0x10 /* drive seek complete */ |
#define | WDCS_DRQ 0x08 /* data request */ |
#define | WDCS_CORR 0x04 /* corrected data */ |
#define | WDCS_IDX 0x02 /* index */ |
#define | WDCS_ERR 0x01 /* error */ |
#define | WDCS_BITS "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" |
#define | WDCE_BBK 0x80 /* bad block detected */ |
#define | WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ |
#define | WDCE_UNC 0x40 /* uncorrectable data error */ |
#define | WDCE_MC 0x20 /* media changed */ |
#define | WDCE_IDNF 0x10 /* id not found */ |
#define | WDCE_MCR 0x08 /* media change requested */ |
#define | WDCE_ABRT 0x04 /* aborted command */ |
#define | WDCE_TK0NF 0x02 /* track 0 not found */ |
#define | WDCE_AMNF 0x01 /* address mark not found */ |
#define | WDCC_NOP 0x00 /* Always fail with "aborted command" */ |
#define | WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
#define | WDCC_READ 0x20 /* disk read code */ |
#define | WDCC_WRITE 0x30 /* disk write code */ |
#define | WDCC__LONG 0x02 /* modifier -- access ecc bytes */ |
#define | WDCC__NORETRY 0x01 /* modifier -- no retrys */ |
#define | WDCC_FORMAT 0x50 /* disk format code */ |
#define | WDCC_DIAGNOSE 0x90 /* controller diagnostic */ |
#define | WDCC_IDP 0x91 /* initialize drive parameters */ |
#define | WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ |
#define | WDCC_READMULTI 0xc4 /* read multiple */ |
#define | WDCC_WRITEMULTI 0xc5 /* write multiple */ |
#define | WDCC_SETMULTI 0xc6 /* set multiple mode */ |
#define | WDCC_READDMA 0xc8 /* read with DMA */ |
#define | WDCC_WRITEDMA 0xca /* write with DMA */ |
#define | WDCC_ACKMC 0xdb /* acknowledge media change */ |
#define | WDCC_LOCK 0xde /* lock drawer */ |
#define | WDCC_UNLOCK 0xdf /* unlock drawer */ |
#define | WDCC_FLUSHCACHE 0xe7 /* Flush cache */ |
#define | WDCC_IDENTIFY 0xec /* read parameters from controller */ |
#define | SET_FEATURES 0xef /* set features */ |
#define | WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ |
#define | WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ |
#define | WDCC_SLEEP 0xe6 /* enter sleep mode */ |
#define | WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ |
#define | WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ |
#define | WDCC_CHECK_PWR 0xe5 /* check power mode */ |
#define | WDCC_SEC_SET_PASSWORD 0xf1 /* set user or master password */ |
#define | WDCC_SEC_UNLOCK 0xf2 /* authenticate */ |
#define | WDCC_SEC_ERASE_PREPARE 0xf3 /* enable device erasing */ |
#define | WDCC_SEC_ERASE_UNIT 0xf4 /* erase all user data */ |
#define | WDCC_SEC_FREEZE_LOCK 0xf5 /* prevent password changes */ |
#define | WDCC_SEC_DISABLE_PASSWORD 0xf6 /* disable lock mode */ |
#define | WDCC_READ_EXT 0x24 /* read 48-bit addressing */ |
#define | WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ |
#define | WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
#define | WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
#define | WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
#define | WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
#define | WDSF_EN_WR_CACHE 0x02 |
#define | WDSF_SET_MODE 0x03 |
#define | WDSF_REASSIGN_EN 0x04 |
#define | WDSF_RETRY_DS 0x33 |
#define | WDSF_SET_CACHE_SGMT 0x54 |
#define | WDSF_READAHEAD_DS 0x55 |
#define | WDSF_POD_DS 0x66 |
#define | WDSF_ECC_DS 0x77 |
#define | WDSF_WRITE_CACHE_DS 0x82 |
#define | WDSF_REASSIGN_DS 0x84 |
#define | WDSF_ECC_EN 0x88 |
#define | WDSF_RETRY_EN 0x99 |
#define | WDSF_SET_CURRENT 0x9a |
#define | WDSF_READAHEAD_EN 0xaa |
#define | WDSF_PREFETCH_SET 0xab |
#define | WDSF_POD_EN 0xcc |
#define | WDSM_RD_DATA 0xd0 |
#define | WDSM_ATTR_AUTOSAVE_EN 0xd2 |
#define | WDSM_SAVE_ATTR 0xd3 |
#define | WDSM_EXEC_OFFL_IMM 0xd4 |
#define | WDSM_ENABLE_OPS 0xd8 |
#define | WDSM_DISABLE_OPS 0xd9 |
#define | WDSM_STATUS 0xda |
#define | WDSMART_CYL_LO 0x4f |
#define | WDSMART_CYL_HI 0xc2 |
#define | WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ |
#define | WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |
#define | WDSD_LBA 0x40 /* logical block addressing */ |
#define | ATAPI_CHECK_POWER_MODE 0xe5 |
#define | ATAPI_EXEC_DRIVE_DIAGS 0x90 |
#define | ATAPI_IDLE_IMMEDIATE 0xe1 |
#define | ATAPI_NOP 0x00 |
#define | ATAPI_PKT_CMD 0xa0 |
#define | ATAPI_IDENTIFY_DEVICE 0xa1 |
#define | ATAPI_SOFT_RESET 0x08 |
#define | ATAPI_SLEEP 0xe6 |
#define | ATAPI_STANDBY_IMMEDIATE 0xe0 |
#define | ATAPI_PKT_CMD_FTRE_DMA 0x01 |
#define | ATAPI_PKT_CMD_FTRE_OVL 0x02 |
#define | WDCI_CMD 0x01 /* command(1) or data(0) */ |
#define | WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
#define | WDCI_RELEASE 0x04 /* bus released until completion */ |
#define | PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) |
#define | PHASE_DATAIN (WDCS_DRQ | WDCI_IN) |
#define | PHASE_DATAOUT (WDCS_DRQ) |
#define | PHASE_COMPLETED (WDCI_IN | WDCI_CMD) |
#define | PHASE_ABORTED (0) |
#define wd_aux_altsts 0 /* alternate fixed disk status (R) */ |
#define wd_aux_ctlr 0 /* fixed disk controller control (W) */ |
#define wd_features 1 /* features (W), same as wd_precomp */ |
#define WDCC_IDENTIFY 0xec /* read parameters from controller */ |
#define WDCC_NOP 0x00 /* Always fail with "aborted command" */ |
#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
#define WDCC_SEC_DISABLE_PASSWORD 0xf6 /* disable lock mode */ |
#define WDCC_SEC_ERASE_PREPARE 0xf3 /* enable device erasing */ |
#define WDCC_SEC_FREEZE_LOCK 0xf5 /* prevent password changes */ |
#define WDCC_SEC_SET_PASSWORD 0xf1 /* set user or master password */ |
#define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ |
#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ |
#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
#define WDCI_RELEASE 0x04 /* bus released until completion */ |
#define WDCS_BITS "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" |
#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |