dev_footbridge.cc Source File

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dev_footbridge.cc
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1 /*
2  * Copyright (C) 2005-2019 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
29  *
30  * TODO:
31  * o) Add actual support for the fcom serial port.
32  * o) FIQs.
33  * o) Pretty much everything else as well :) (This entire thing
34  * is a quick hack to work primarily with NetBSD and OpenBSD
35  * as guest OSes.)
36  */
37 
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <string.h>
41 
42 #include "bus_pci.h"
43 #include "console.h"
44 #include "cpu.h"
45 #include "device.h"
46 #include "devices.h"
47 #include "machine.h"
48 #include "memory.h"
49 #include "misc.h"
50 #include "timer.h"
51 
52 #include "thirdparty/dc21285reg.h"
53 
54 
55 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
56 #define DEV_FOOTBRIDGE_LENGTH 0x400
57 
58 #define N_FOOTBRIDGE_TIMERS 4
59 
61  struct interrupt irq;
62 
63  struct pci_data *pcibus;
64 
66 
70 
74 
76 
77  uint32_t irq_status;
78  uint32_t irq_enable;
79 
80  uint32_t fiq_status;
81  uint32_t fiq_enable;
82 };
83 
84 
85 static void timer_tick0(struct timer *t, void *extra)
86 { ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
87 static void timer_tick1(struct timer *t, void *extra)
88 { ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
89 static void timer_tick2(struct timer *t, void *extra)
90 { ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
91 static void timer_tick3(struct timer *t, void *extra)
92 { ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
93 
94 
95 static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
96  int timer_nr)
97 {
98  double freq = (double)cpu->machine->emulated_hz;
99  int cycles = d->timer_load[timer_nr];
100 
101  if (d->timer_control[timer_nr] & TIMER_FCLK_16)
102  cycles <<= 4;
103  else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
104  cycles <<= 8;
105  freq /= (double)cycles;
106 
107  d->timer_value[timer_nr] = d->timer_load[timer_nr];
108 
109  /* printf("%i: %i -> %f Hz\n", timer_nr,
110  d->timer_load[timer_nr], freq); */
111 
112  if (d->timer[timer_nr] == NULL) {
113  switch (timer_nr) {
114  case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break;
115  case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break;
116  case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break;
117  case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break;
118  }
119  } else {
120  timer_update_frequency(d->timer[timer_nr], freq);
121  }
122 }
123 
124 
125 /*
126  * The 4 footbridge timers should decrease and cause interrupts. Periodic
127  * interrupts restart as soon as they are acknowledged, non-periodic
128  * interrupts need to be "reloaded" to restart.
129  *
130  * TODO: Hm. I thought I had solved this, but it didn't quite work.
131  * This needs to be re-checked against documentation, sometime.
132  */
133 DEVICE_TICK(footbridge)
134 {
135  struct footbridge_data *d = (struct footbridge_data *) extra;
136  int i;
137 
138  for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
139  if (d->timer_control[i] & TIMER_ENABLE) {
140  if (d->pending_timer_interrupts[i] > 0) {
141  d->timer_value[i] = random() % d->timer_load[i];
143  }
144  }
145  }
146 }
147 
148 
149 /*
150  * footbridge_interrupt_assert():
151  */
153 {
154  struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
155  d->irq_status |= interrupt->line;
156 
157  // Patch from NetBSD:
158  // "fix hang interrupt issue. Always assert the irq's even if we have
159  // already asserted the global irq for the device. prevents hangs with
160  // cats."
161  if ((d->irq_status & d->irq_enable) /* && !d->irq_asserted */) {
162  d->irq_asserted = 1;
163  INTERRUPT_ASSERT(d->irq);
164  }
165 }
166 
167 
168 /*
169  * footbridge_interrupt_deassert():
170  */
172 {
173  struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
174  d->irq_status &= ~interrupt->line;
175 
176  if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
177  d->irq_asserted = 0;
179  }
180 }
181 
182 
183 /*
184  * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
185  * interrupt has occurred (and acknowledging it at the same time), than
186  * dealing with the legacy 0x20/0xa0 ISA ports.
187  */
188 DEVICE_ACCESS(footbridge_isa)
189 {
190  /* struct footbridge_data *d = extra; */
191  uint64_t idata = 0, odata = 0;
192  int x;
193 
194  if (writeflag == MEM_WRITE) {
195  idata = memory_readmax64(cpu, data, len);
196  fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
197  }
198 
200  if (x < 8)
201  odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
202  else
203  odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
204 
205  if (writeflag == MEM_READ)
206  memory_writemax64(cpu, data, len, odata);
207 
208  return 1;
209 }
210 
211 
212 /*
213  * Reset pin at ISA port 0x338, at least in the NetWinder:
214  *
215  * TODO: NOT WORKING YET!
216  */
217 DEVICE_ACCESS(footbridge_reset)
218 {
219  uint64_t idata = 0;
220 
221  if (writeflag == MEM_WRITE) {
222  idata = memory_readmax64(cpu, data, len);
223  if (idata & 0x40) {
224  debug("[ footbridge_reset: GP16: Halting. ]\n");
225  cpu->running = 0;
226 exit(1);
227  }
228  }
229 
230  return 1;
231 }
232 
233 
234 /*
235  * The Footbridge PCI configuration space is implemented as a direct memory
236  * space (i.e. not one port for addr and one port for data). This function
237  * translates that into bus_pci calls.
238  */
239 DEVICE_ACCESS(footbridge_pci)
240 {
241  struct footbridge_data *d = (struct footbridge_data *) extra;
242  uint64_t idata = 0, odata = 0;
243  int bus, dev, func, reg;
244 
245  if (writeflag == MEM_WRITE)
247 
248  /* Decompose the (direct) address into its components: */
249  bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
250  bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
251 
252  if (bus == 255) {
253  fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
254  " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
255  exit(1);
256  }
257 
258  debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
259  "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
260  dev, func, reg);
261 
262  bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
263  &odata : &idata, len, writeflag);
264 
265  if (writeflag == MEM_READ)
267 
268  return 1;
269 }
270 
271 
272 DEVICE_ACCESS(footbridge)
273 {
274  struct footbridge_data *d = (struct footbridge_data *) extra;
275  uint64_t idata = 0, odata = 0;
276  int timer_nr = 0;
277 
278  if (writeflag == MEM_WRITE)
279  idata = memory_readmax64(cpu, data, len);
280 
281  if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
282  timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
283  relative_addr &= ~0x060;
284  }
285 
286  switch (relative_addr) {
287 
288  case VENDOR_ID:
289  odata = 0x1011; /* DC21285_VENDOR_ID */
290  break;
291 
292  case DEVICE_ID:
293  odata = 0x1065; /* DC21285_DEVICE_ID */
294  break;
295 
296  case 0x04:
297  case 0x0c:
298  case 0x10:
299  case 0x14:
300  case 0x18:
301  /* TODO. Written to by Linux. */
302  break;
303 
304  case REVISION:
305  odata = 3; /* footbridge revision number */
306  break;
307 
309  /* TODO: Written to by Linux. */
310  if (writeflag == MEM_WRITE && idata != 0)
311  fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
312  "EXTENSION: 0x%llx ]\n", (long long)idata);
313  break;
314 
315  case SA_CONTROL:
316  /* Read by Linux: */
317  odata = PCI_CENTRAL_FUNCTION;
318  break;
319 
320  case UART_DATA:
321  if (writeflag == MEM_WRITE)
322  console_putchar(d->console_handle, idata);
323  break;
324 
325  case UART_RX_STAT:
326  /* TODO */
327  odata = 0;
328  break;
329 
330  case UART_FLAGS:
331  odata = UART_TX_EMPTY;
332  break;
333 
334  case IRQ_STATUS:
335  if (writeflag == MEM_READ)
336  odata = d->irq_status & d->irq_enable;
337  else {
338  fatal("[ WARNING: footbridge write to irq status? ]\n");
339  exit(1);
340  }
341  break;
342 
343  case IRQ_RAW_STATUS:
344  if (writeflag == MEM_READ)
345  odata = d->irq_status;
346  else {
347  fatal("[ footbridge write to irq_raw_status ]\n");
348  exit(1);
349  }
350  break;
351 
352  case IRQ_ENABLE_SET:
353  if (writeflag == MEM_WRITE) {
354  d->irq_enable |= idata;
355  if (d->irq_status & d->irq_enable)
356  INTERRUPT_ASSERT(d->irq);
357  else
359  } else {
360  odata = d->irq_enable;
361  fatal("[ WARNING: footbridge read from "
362  "ENABLE SET? ]\n");
363  exit(1);
364  }
365  break;
366 
367  case IRQ_ENABLE_CLEAR:
368  if (writeflag == MEM_WRITE) {
369  d->irq_enable &= ~idata;
370  if (d->irq_status & d->irq_enable)
371  INTERRUPT_ASSERT(d->irq);
372  else
374  } else {
375  odata = d->irq_enable;
376  fatal("[ WARNING: footbridge read from "
377  "ENABLE CLEAR? ]\n");
378  exit(1);
379  }
380  break;
381 
382  case FIQ_STATUS:
383  if (writeflag == MEM_READ)
384  odata = d->fiq_status & d->fiq_enable;
385  else {
386  fatal("[ WARNING: footbridge write to fiq status? ]\n");
387  exit(1);
388  }
389  break;
390 
391  case FIQ_RAW_STATUS:
392  if (writeflag == MEM_READ)
393  odata = d->fiq_status;
394  else {
395  fatal("[ footbridge write to fiq_raw_status ]\n");
396  exit(1);
397  }
398  break;
399 
400  case FIQ_ENABLE_SET:
401  if (writeflag == MEM_WRITE)
402  d->fiq_enable |= idata;
403  break;
404 
405  case FIQ_ENABLE_CLEAR:
406  if (writeflag == MEM_WRITE)
407  d->fiq_enable &= ~idata;
408  break;
409 
410  case TIMER_1_LOAD:
411  if (writeflag == MEM_READ)
412  odata = d->timer_load[timer_nr];
413  else {
414  d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
415  reload_timer_value(cpu, d, timer_nr);
416  /* debug("[ footbridge: timer %i (1-based), "
417  "value %i ]\n", timer_nr + 1,
418  (int)d->timer_value[timer_nr]); */
419  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
420  }
421  break;
422 
423  case TIMER_1_VALUE:
424  if (writeflag == MEM_READ)
425  odata = d->timer_value[timer_nr];
426  else
427  d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
428  break;
429 
430  case TIMER_1_CONTROL:
431  if (writeflag == MEM_READ)
432  odata = d->timer_control[timer_nr];
433  else {
434  d->timer_control[timer_nr] = idata;
435  if (idata & TIMER_FCLK_16 &&
436  idata & TIMER_FCLK_256) {
437  fatal("TODO: footbridge timer: "
438  "both 16 and 256?\n");
439  exit(1);
440  }
441  if (idata & TIMER_ENABLE) {
442  reload_timer_value(cpu, d, timer_nr);
443  } else {
444  d->pending_timer_interrupts[timer_nr] = 0;
445  }
446  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
447  }
448  break;
449 
450  case TIMER_1_CLEAR:
451  if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
452  reload_timer_value(cpu, d, timer_nr);
453  }
454 
455  if (d->pending_timer_interrupts[timer_nr] > 0) {
456  d->pending_timer_interrupts[timer_nr] --;
457  }
458 
459  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
460  break;
461 
462  case SDRAM_BA_MASK:
463  if (writeflag == MEM_READ) {
464  fatal("[ footbridge read from sdram_ba_mask ]\n");
465  exit(1);
466  } else {
467  switch (idata) {
468  case SDRAM_MASK_256KB:
469  case SDRAM_MASK_512KB:
470  case SDRAM_MASK_1MB:
471  case SDRAM_MASK_2MB:
472  case SDRAM_MASK_4MB:
473  case SDRAM_MASK_8MB:
474  case SDRAM_MASK_16MB:
475  case SDRAM_MASK_32MB:
476  case SDRAM_MASK_64MB:
477  case SDRAM_MASK_128MB:
478  case SDRAM_MASK_256MB:
479  break;
480  default:
481  fatal("[ footbridge write to sdram_ba_mask "
482  "%#llx ]\n", (long long)idata);
483  break;
484  }
485  }
486  break;
487  case SDRAM_BA_OFFSET:
488  if (writeflag == MEM_READ) {
489  fatal("[ footbridge read from sdram_ba_offset ]\n");
490  exit(1);
491  } else {
492  if (idata != 0)
493  fatal("[ footbridge write to sdram_ba_offset "
494  "%#llx ]\n", (long long)idata);
495  }
496  break;
497 
498  default:if (writeflag == MEM_READ) {
499  fatal("[ footbridge: read from 0x%x ]\n",
500  (int)relative_addr);
501  } else {
502  fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
503  (int)relative_addr, (long long)idata);
504  }
505  }
506 
507  if (writeflag == MEM_READ)
508  memory_writemax64(cpu, data, len, odata);
509 
510  return 1;
511 }
512 
513 
514 DEVINIT(footbridge)
515 {
516  struct footbridge_data *d;
517  char irq_path[300], irq_path_isa[400];
518  uint64_t pci_addr = 0x7b000000;
519  int i;
520 
521  CHECK_ALLOCATION(d = (struct footbridge_data *) malloc(sizeof(struct footbridge_data)));
522  memset(d, 0, sizeof(struct footbridge_data));
523 
524  /* Connect to the CPU which this footbridge will interrupt: */
526 
527  /* DC21285 register access: */
530  dev_footbridge_access, d, DM_DEFAULT, NULL);
531 
532  /* ISA interrupt status/acknowledgement: */
533  memory_device_register(devinit->machine->memory, "footbridge_isa",
534  0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
535 
536  /* The "fcom" console: */
538 
539  /* Register 32 footbridge interrupts: */
540  snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
542  for (i=0; i<32; i++) {
543  struct interrupt interrupt_template;
544  char tmpstr[600];
545 
546  memset(&interrupt_template, 0, sizeof(interrupt_template));
547  interrupt_template.line = 1 << i;
548  snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
549  interrupt_template.name = tmpstr;
550 
551  interrupt_template.extra = d;
552  interrupt_template.interrupt_assert =
554  interrupt_template.interrupt_deassert =
556  interrupt_handler_register(&interrupt_template);
557 
558  /* Connect locally to some interrupts: */
559  if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
560  INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
561  }
562 
563  switch (devinit->machine->machine_type) {
564  case MACHINE_CATS:
565  snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
566  break;
567  case MACHINE_NETWINDER:
568  snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
569  break;
570  default:fatal("footbridge unimpl machine type\n");
571  exit(1);
572  }
573 
574  /* A PCI bus: */
575  d->pcibus = bus_pci_init(
576  devinit->machine,
577  irq_path,
578  0x7c000000, /* PCI device io offset */
579  0x80000000, /* PCI device mem offset */
580  0x00000000, /* PCI port base */
581  0x00000000, /* PCI mem base */
582  irq_path, /* PCI irq base */
583  0x7c000000, /* ISA port base */
584  0x80000000, /* ISA mem base */
585  irq_path_isa); /* ISA port base */
586 
587  /* ... with some default devices for known machine types: */
588  switch (devinit->machine->machine_type) {
589  case MACHINE_CATS:
591  devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
593  devinit->machine->memory, 0xc0, 10, 0, "dec21143");
595  devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
596  break;
597  case MACHINE_NETWINDER:
599  devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
601  devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
603  "footbridge_reset", 0x7c000338, 1,
604  dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
605  break;
606  default:fatal("footbridge: unimplemented machine type.\n");
607  exit(1);
608  }
609 
610  /* PCI configuration space: */
612  "footbridge_pci", pci_addr, 0x1000000,
613  dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
614 
615  /* Timer ticks: */
616  for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
618  d->timer_load[i] = TIMER_MAX_VAL;
619  }
620 
622  dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
623 
624  devinit->return_ptr = d->pcibus;
625  return 1;
626 }
627 
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Definition: device.h:41
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int last_int
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Definition: dev_footbridge.cc:55
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Definition: dc21285reg.h:304
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Definition: dev_footbridge.cc:68
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Definition: dc21285reg.h:197
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void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:76
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struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:355
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Definition: dc21285reg.h:140
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Definition: memory.h:117
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Definition: dc21285reg.h:363
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Definition: dev_footbridge.cc:65
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Definition: machine.cc:280
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Definition: dev_footbridge.cc:78
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Definition: device.h:50
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uint32_t timer_load[N_FOOTBRIDGE_TIMERS]
Definition: dev_footbridge.cc:67
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Definition: main.cc:152
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Definition: dc21285reg.h:151
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Definition: dev_footbridge.cc:188
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Definition: dc21285reg.h:343
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uint32_t fiq_enable
Definition: dev_footbridge.cc:81
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struct isa_pic_data isa_pic_data
Definition: machine.h:190
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Definition: machine.h:241
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Definition: dc21285reg.h:150
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int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS]
Definition: dev_footbridge.cc:73
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Definition: dc21285reg.h:366
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Definition: dev_footbridge.cc:133
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Definition: dc21285reg.h:293
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Definition: dc21285reg.h:49
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Definition: device.h:40
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Definition: dc21285reg.h:390
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Definition: console.cc:673
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Definition: dc21285reg.h:362
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Definition: dev_footbridge.cc:71
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Definition: dc21285reg.h:51
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Definition: machine.h:126
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Definition: dc21285reg.h:376
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Definition: cpu.h:328
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Definition: tmp_alpha_tail.cc:53
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Definition: dc21285reg.h:333
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Definition: dc21285reg.h:222
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Definition: dc21285reg.h:342
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Definition: dev_footbridge.cc:75
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Definition: timer.cc:132
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void footbridge_interrupt_assert(struct interrupt *interrupt)
Definition: dev_footbridge.cc:152
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Definition: dc21285reg.h:377
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Definition: interrupt.h:75
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Definition: dc21285reg.h:144
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Definition: machine.h:111
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Definition: interrupt.h:51
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Definition: machine.h:165
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Definition: dc21285reg.h:148
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Definition: interrupt.h:38
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Definition: interrupt.cc:81
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Definition: interrupt.h:66
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Definition: dc21285reg.h:335
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Definition: dc21285reg.h:332
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Definition: interrupt.h:36
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Definition: dc21285reg.h:301
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Definition: memory.cc:89
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Definition: dc21285reg.h:378
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Definition: dc21285reg.h:339
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Definition: cpu.h:326
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Definition: dc21285reg.h:142
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Definition: bus_pci.cc:216
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Definition: cpu.h:386
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Definition: dev_footbridge.cc:63
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Definition: dc21285reg.h:367
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Definition: dev_footbridge.cc:72
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Definition: timer.cc:50
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Definition: misc.h:239

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