sh4_cache.h Source File
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3 #ifndef _SH3_CACHE_SH4_H_
4 #define _SH3_CACHE_SH4_H_
49 #define SH4_ICACHE_SIZE 8192
50 #define SH4_DCACHE_SIZE 16384
51 #define SH4_EMODE_ICACHE_SIZE 16384
52 #define SH4_EMODE_DCACHE_SIZE 32768
53 #define SH4_CACHE_LINESZ 32
55 #define SH4_CCR 0xff00001c
56 #define SH4_CCR_EMODE 0x80000000
57 #define SH4_CCR_IIX 0x00008000
58 #define SH4_CCR_ICI 0x00000800
59 #define SH4_CCR_ICE 0x00000100
60 #define SH4_CCR_OIX 0x00000080
61 #define SH4_CCR_ORA 0x00000020
62 #define SH4_CCR_OCI 0x00000008
63 #define SH4_CCR_CB 0x00000004
64 #define SH4_CCR_WT 0x00000002
65 #define SH4_CCR_OCE 0x00000001
67 #define SH4_QACR0 0xff000038
68 #define SH4_QACR1 0xff00003c
69 #define SH4_QACR_AREA_SHIFT 2
70 #define SH4_QACR_AREA_MASK 0x0000001c
73 #define SH4_CCIA 0xf0000000
75 #define CCIA_A 0x00000008
76 #define CCIA_ENTRY_SHIFT 5
77 #define CCIA_ENTRY_MASK 0x00001fe0
78 #define CCIA_EMODE_ENTRY_MASK 0x00003fe0
80 #define CCIA_V 0x00000001
81 #define CCIA_TAGADDR_MASK 0xfffffc00
83 #define SH4_CCID 0xf1000000
85 #define CCID_L_SHIFT 2
86 #define CCID_L_MASK 0x1c
87 #define CCID_ENTRY_MASK 0x00001fe0
90 #define SH4_CCDA 0xf4000000
92 #define CCDA_A 0x00000008
93 #define CCDA_ENTRY_SHIFT 5
94 #define CCDA_ENTRY_MASK 0x00003fe0
96 #define CCDA_V 0x00000001
97 #define CCDA_U 0x00000002
98 #define CCDA_TAGADDR_MASK 0xfffffc00
100 #define SH4_CCDD 0xf5000000
103 #define SH4_SQ 0xe0000000
108 #define SH4_CACHE_FLUSH() \
113 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
114 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
115 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
118 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
119 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
120 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \
124 #define SH4_EMODE_CACHE_FLUSH() \
129 for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
130 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
131 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
134 for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
135 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
136 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \
140 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH()
141 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH()
142 #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH()
143 #if defined(SH4_CACHE_DISABLE_EMODE)
144 #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH()
145 #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH()
147 #define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
148 #define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
153 extern void sh4_cache_config(
void);
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