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Macros | |
#define | P5064_MEMORY 0x00000000UL /* onboard DRAM memory */ |
#define | P5064_ISAMEM 0x10000000UL /* ISA window of PCI memory */ |
#define | P5064_PCIMEM 0x11000000UL /* PCI memory window */ |
#define | P5064_PCIIO 0x1d000000UL /* PCI I/O window */ |
#define | P5064_PCICFG 0x1ee00000UL /* PCI config space */ |
#define | P5064_V360EPC 0x1ef00000UL /* V360EPC PCI controller */ |
#define | P5064_CFGBOOT_W 0x1f800000UL /* configured bootstrap (W) */ |
#define | P5064_SOCKET_W 0x1f900000UL /* socket EPROM (W) */ |
#define | P5064_FLASH_W 0x1fa00000UL /* flash (W) */ |
#define | P5064_CFBOOT 0x1fc00000UL /* configured bootstrap */ |
#define | P5064_SOCKET 0x1fd00000UL /* socket EPROM */ |
#define | P5064_FLASH 0x1fe00000UL /* flash */ |
#define | P5064_LED0 0x1ff00000UL /* LED (1reg) */ |
#define | P5064_LED1 0x1ff20010UL /* LED (4reg) */ |
#define | P5064_LCD 0x1ff30000UL /* LCD display */ |
#define | P5064_Z80GPIO 0x1ff40000UL /* Z80 GPIO (rev B only) */ |
#define | P5064_Z80GPIO_IACK 0x1ff50000UL /* intr. ack. for Z80 */ |
#define | P5064_DBG_UART 0x1ff60000UL /* UART on debug board */ |
#define | P5064_LOCINT 0x1ff90000UL /* local interrupts */ |
#define | P5064_PANIC 0x1ff90004UL /* panic interrupts */ |
#define | P5064_PCIINT 0x1ff90008UL /* PCI interrupts */ |
#define | P5064_ISAINT 0x1ff9000cUL /* ISA interrupts */ |
#define | P5064_XBAR0 0x1ff90010UL /* Int. xbar 0 */ |
#define | P5064_XBAR1 0x1ff90014UL /* Int. xbar 1 */ |
#define | P5064_XBAR2 0x1ff90018UL /* Int. xbar 2 */ |
#define | P5064_XBAR3 0x1ff9001cUL /* Int. xbar 3 */ |
#define | P5064_XBAR4 0x1ff90020UL /* Int. xbar 4 */ |
#define | P5064_KBDINT 0x1ff90024UL /* keyboard interrupts */ |
#define | P5064_LOGICREV 0x1ff9003cUL /* logic revision */ |
#define | P5064_CFG0 0x1ffa0000UL /* board configuration 0 */ |
#define | P5064_CFG1 0x1ffb0000UL /* board configuration 1 */ |
#define | P5064_DRAMCFG 0x1ffc0000UL /* DRAM configuration */ |
#define | P5064_BOARDREV 0x1ffd0000UL /* board revision */ |
#define | P5064_PCIMEM_HI 0x20000000UL /* PCI memory high window */ |
#define | LOCINT_PCIBR 0x01 |
#define | LOCINT_FLP 0x02 |
#define | LOCINT_MKBD 0x04 |
#define | LOCINT_COM1 0x08 |
#define | LOCINT_COM2 0x10 |
#define | LOCINT_CENT 0x20 |
#define | LOCINT_RTC 0x80 |
#define | PANIC_DEBUG 0x01 |
#define | PANIC_PFAIL 0x02 |
#define | PANIC_BERR 0x04 |
#define | PANIC_ISANMI 0x08 |
#define | PANIC_IOPERR 0x10 |
#define | PANIC_CENT 0x20 |
#define | PANIC_EWAKE 0x40 |
#define | PANIC_ECODERR 0x80 |
#define | PCIINT_EMDINT 0x01 |
#define | PCIINT_ETH 0x02 |
#define | PCIINT_SCSI 0x04 |
#define | PCIINT_USB 0x08 |
#define | PCIINT_PCI0 0x10 |
#define | PCIINT_PCI1 0x20 |
#define | PCIINT_PCI2 0x40 |
#define | PCIINT_PCI3 0x80 |
#define | ISAINT_ISABR 0x01 |
#define | ISAINT_IDE0 0x02 |
#define | ISAINT_IDE1 0x04 |
#define | KBDINT_KBD 0x01 |
#define | KBDINT_MOUSE 0x02 |
#define | P5064_DMA_ISA_PCIBASE 0x00800000UL |
#define | P5064_DMA_ISA_PHYSBASE 0x00000000UL |
#define | P5064_DMA_ISA_SIZE (8 * 1024 * 1024) |
#define | P5064_DMA_PCI_PCIBASE 0x80000000UL |
#define | P5064_DMA_PCI_PHYSBASE 0x00000000UL |
#define | P5064_DMA_PCI_SIZE (256 * 1024 * 1024) |
#define ISAINT_IDE0 0x02 |
Definition at line 127 of file algor_p5064reg.h.
#define ISAINT_IDE1 0x04 |
Definition at line 128 of file algor_p5064reg.h.
#define ISAINT_ISABR 0x01 |
Definition at line 126 of file algor_p5064reg.h.
#define KBDINT_KBD 0x01 |
Definition at line 131 of file algor_p5064reg.h.
#define KBDINT_MOUSE 0x02 |
Definition at line 132 of file algor_p5064reg.h.
#define LOCINT_CENT 0x20 |
Definition at line 102 of file algor_p5064reg.h.
#define LOCINT_COM1 0x08 |
Definition at line 100 of file algor_p5064reg.h.
#define LOCINT_COM2 0x10 |
Definition at line 101 of file algor_p5064reg.h.
#define LOCINT_FLP 0x02 |
Definition at line 98 of file algor_p5064reg.h.
#define LOCINT_MKBD 0x04 |
Definition at line 99 of file algor_p5064reg.h.
#define LOCINT_PCIBR 0x01 |
Definition at line 97 of file algor_p5064reg.h.
#define LOCINT_RTC 0x80 |
Definition at line 103 of file algor_p5064reg.h.
#define P5064_BOARDREV 0x1ffd0000UL /* board revision */ |
Definition at line 92 of file algor_p5064reg.h.
#define P5064_CFBOOT 0x1fc00000UL /* configured bootstrap */ |
Definition at line 66 of file algor_p5064reg.h.
#define P5064_CFG0 0x1ffa0000UL /* board configuration 0 */ |
Definition at line 89 of file algor_p5064reg.h.
#define P5064_CFG1 0x1ffb0000UL /* board configuration 1 */ |
Definition at line 90 of file algor_p5064reg.h.
#define P5064_CFGBOOT_W 0x1f800000UL /* configured bootstrap (W) */ |
Definition at line 60 of file algor_p5064reg.h.
#define P5064_DBG_UART 0x1ff60000UL /* UART on debug board */ |
Definition at line 77 of file algor_p5064reg.h.
#define P5064_DMA_ISA_PCIBASE 0x00800000UL |
Definition at line 145 of file algor_p5064reg.h.
#define P5064_DMA_ISA_PHYSBASE 0x00000000UL |
Definition at line 146 of file algor_p5064reg.h.
#define P5064_DMA_ISA_SIZE (8 * 1024 * 1024) |
Definition at line 147 of file algor_p5064reg.h.
#define P5064_DMA_PCI_PCIBASE 0x80000000UL |
Definition at line 149 of file algor_p5064reg.h.
#define P5064_DMA_PCI_PHYSBASE 0x00000000UL |
Definition at line 150 of file algor_p5064reg.h.
#define P5064_DMA_PCI_SIZE (256 * 1024 * 1024) |
Definition at line 151 of file algor_p5064reg.h.
#define P5064_DRAMCFG 0x1ffc0000UL /* DRAM configuration */ |
Definition at line 91 of file algor_p5064reg.h.
#define P5064_FLASH 0x1fe00000UL /* flash */ |
Definition at line 70 of file algor_p5064reg.h.
#define P5064_FLASH_W 0x1fa00000UL /* flash (W) */ |
Definition at line 64 of file algor_p5064reg.h.
#define P5064_ISAINT 0x1ff9000cUL /* ISA interrupts */ |
Definition at line 81 of file algor_p5064reg.h.
#define P5064_ISAMEM 0x10000000UL /* ISA window of PCI memory */ |
Definition at line 50 of file algor_p5064reg.h.
#define P5064_KBDINT 0x1ff90024UL /* keyboard interrupts */ |
Definition at line 87 of file algor_p5064reg.h.
#define P5064_LCD 0x1ff30000UL /* LCD display */ |
Definition at line 74 of file algor_p5064reg.h.
#define P5064_LED0 0x1ff00000UL /* LED (1reg) */ |
Definition at line 72 of file algor_p5064reg.h.
#define P5064_LED1 0x1ff20010UL /* LED (4reg) */ |
Definition at line 73 of file algor_p5064reg.h.
#define P5064_LOCINT 0x1ff90000UL /* local interrupts */ |
Definition at line 78 of file algor_p5064reg.h.
#define P5064_LOGICREV 0x1ff9003cUL /* logic revision */ |
Definition at line 88 of file algor_p5064reg.h.
#define P5064_MEMORY 0x00000000UL /* onboard DRAM memory */ |
Definition at line 48 of file algor_p5064reg.h.
#define P5064_PANIC 0x1ff90004UL /* panic interrupts */ |
Definition at line 79 of file algor_p5064reg.h.
#define P5064_PCICFG 0x1ee00000UL /* PCI config space */ |
Definition at line 56 of file algor_p5064reg.h.
#define P5064_PCIINT 0x1ff90008UL /* PCI interrupts */ |
Definition at line 80 of file algor_p5064reg.h.
#define P5064_PCIIO 0x1d000000UL /* PCI I/O window */ |
Definition at line 54 of file algor_p5064reg.h.
#define P5064_PCIMEM 0x11000000UL /* PCI memory window */ |
Definition at line 52 of file algor_p5064reg.h.
#define P5064_PCIMEM_HI 0x20000000UL /* PCI memory high window */ |
Definition at line 93 of file algor_p5064reg.h.
#define P5064_SOCKET 0x1fd00000UL /* socket EPROM */ |
Definition at line 68 of file algor_p5064reg.h.
#define P5064_SOCKET_W 0x1f900000UL /* socket EPROM (W) */ |
Definition at line 62 of file algor_p5064reg.h.
#define P5064_V360EPC 0x1ef00000UL /* V360EPC PCI controller */ |
Definition at line 58 of file algor_p5064reg.h.
#define P5064_XBAR0 0x1ff90010UL /* Int. xbar 0 */ |
Definition at line 82 of file algor_p5064reg.h.
#define P5064_XBAR1 0x1ff90014UL /* Int. xbar 1 */ |
Definition at line 83 of file algor_p5064reg.h.
#define P5064_XBAR2 0x1ff90018UL /* Int. xbar 2 */ |
Definition at line 84 of file algor_p5064reg.h.
#define P5064_XBAR3 0x1ff9001cUL /* Int. xbar 3 */ |
Definition at line 85 of file algor_p5064reg.h.
#define P5064_XBAR4 0x1ff90020UL /* Int. xbar 4 */ |
Definition at line 86 of file algor_p5064reg.h.
#define P5064_Z80GPIO 0x1ff40000UL /* Z80 GPIO (rev B only) */ |
Definition at line 75 of file algor_p5064reg.h.
#define P5064_Z80GPIO_IACK 0x1ff50000UL /* intr. ack. for Z80 */ |
Definition at line 76 of file algor_p5064reg.h.
#define PANIC_BERR 0x04 |
Definition at line 108 of file algor_p5064reg.h.
#define PANIC_CENT 0x20 |
Definition at line 111 of file algor_p5064reg.h.
#define PANIC_DEBUG 0x01 |
Definition at line 106 of file algor_p5064reg.h.
#define PANIC_ECODERR 0x80 |
Definition at line 113 of file algor_p5064reg.h.
#define PANIC_EWAKE 0x40 |
Definition at line 112 of file algor_p5064reg.h.
#define PANIC_IOPERR 0x10 |
Definition at line 110 of file algor_p5064reg.h.
#define PANIC_ISANMI 0x08 |
Definition at line 109 of file algor_p5064reg.h.
#define PANIC_PFAIL 0x02 |
Definition at line 107 of file algor_p5064reg.h.
#define PCIINT_EMDINT 0x01 |
Definition at line 116 of file algor_p5064reg.h.
#define PCIINT_ETH 0x02 |
Definition at line 117 of file algor_p5064reg.h.
#define PCIINT_PCI0 0x10 |
Definition at line 120 of file algor_p5064reg.h.
#define PCIINT_PCI1 0x20 |
Definition at line 121 of file algor_p5064reg.h.
#define PCIINT_PCI2 0x40 |
Definition at line 122 of file algor_p5064reg.h.
#define PCIINT_PCI3 0x80 |
Definition at line 123 of file algor_p5064reg.h.
#define PCIINT_SCSI 0x04 |
Definition at line 118 of file algor_p5064reg.h.
#define PCIINT_USB 0x08 |
Definition at line 119 of file algor_p5064reg.h.