dev_sh4.cc Source File

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dev_sh4.cc
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1 /*
2  * Copyright (C) 2006-2019 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
29  *
30  * TODO: Among other things:
31  *
32  * x) Interrupt masks (msk register stuff). Are these really correct?
33  * x) BSC (Bus state controller).
34  * x) DMA: Right now there's a hack for Dreamcast emulation
35  * x) UBC (User Break Controller)
36  * x) ...
37  */
38 
39 #include <stdio.h>
40 #include <stdlib.h>
41 #include <string.h>
42 
43 #include "bus_pci.h"
44 #include "console.h"
45 #include "cpu.h"
46 #include "device.h"
47 #include "devices.h"
48 #include "interrupt.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52 #include "sh4_dmacreg.h"
53 #include "timer.h"
54 
55 #include "thirdparty/sh4_bscreg.h"
56 #include "thirdparty/sh4_cache.h"
58 #include "thirdparty/sh4_intcreg.h"
59 #include "thirdparty/sh4_mmu.h"
60 #include "thirdparty/sh4_pcicreg.h"
61 #include "thirdparty/sh4_rtcreg.h"
62 #include "thirdparty/sh4_scifreg.h"
63 #include "thirdparty/sh4_scireg.h"
64 #include "thirdparty/sh4_tmureg.h"
65 
66 
67 #define SH4_REG_BASE 0xff000000
68 #define SH4_TICK_SHIFT 14
69 #define N_SH4_TIMERS 3
70 
71 /* PCI stuff: */
72 #define N_PCIC_REGS (0x224 / sizeof(uint32_t))
73 #define N_PCIC_IRQS 16
74 #define PCIC_REG(addr) ((addr - SH4_PCIC) / sizeof(uint32_t))
75 #define PCI_VENDOR_HITACHI 0x1054
76 #define PCI_PRODUCT_HITACHI_SH7751 0x3505
77 #define PCI_PRODUCT_HITACHI_SH7751R 0x350e
78 
79 #define SCIF_TX_FIFO_SIZE 16
80 #define SCIF_DELAYED_TX_VALUE 2 /* 2 to be safe, 1 = fast but buggy */
81 
82 #ifdef UNSTABLE_DEVEL
83 // #define SH4_DEBUG
84 /* #define debug fatal */
85 #endif
86 
87 // Clock/occilation related
88 #define SH4_CPG_FRQCR 0xffc00000 /* 16-bit */
89 #define SH4_CPG_STBCR 0xffc00004 /* 8-bit */
90 #define SH4_CPG_WTCNT 0xffc00008 /* 8/16-bit */
91 #define SH4_CPG_WTCSR 0xffc0000c /* 8/16-bit */
92 #define SH4_CPG_STBCR2 0xffc00010 /* 8-bit */
93 
94 
95 struct sh4_data {
96  /* Store Queues: */
97  uint8_t sq[32 * 2];
98 
99  /* SCIF (Serial controller): */
100  uint16_t scif_smr;
101  uint8_t scif_brr;
102  uint16_t scif_scr;
103  uint16_t scif_ssr;
104  uint16_t scif_fcr;
105  uint16_t scif_lsr;
110  struct interrupt scif_tx_irq;
111  struct interrupt scif_rx_irq;
114 
115  /* Bus State Controller: */
116  uint32_t bsc_bcr1;
117  uint16_t bsc_bcr2;
118  uint16_t bsc_bcr3; /* SH7751R */
119  uint32_t bsc_wcr1;
120  uint32_t bsc_wcr2;
121  uint32_t bsc_wcr3;
122  uint32_t bsc_mcr;
123  uint16_t bsc_pcr;
124  uint16_t bsc_rtcsr;
125  uint16_t bsc_rtcor;
126  uint16_t bsc_rfcr;
127 
128  /* CPG: */
129  uint16_t cpg_frqcr;
130  uint8_t cpg_stbcr;
131  uint16_t cpg_wtcnt;
132  uint16_t cpg_wtcsr;
133  uint8_t cpg_stbcr2;
134 
135  /* GPIO: */
136  uint32_t pctra; /* Port Control Register A */
137  uint32_t pdtra; /* Port Data Register A */
138  uint32_t pctrb; /* Port Control Register B */
139  uint32_t pdtrb; /* Port Data Register B */
140  uint16_t bsc_gpioic;
141 
142  /* PCIC (PCI controller): */
146 
147  /* SCI (serial interface): */
150  uint8_t sci_scsptr;
151  uint8_t sci_curbyte;
152  uint8_t sci_cur_addr;
153 
154  /* SD-RAM: */
155  uint16_t sdmr2;
156  uint16_t sdmr3;
157 
158  /* Timer Management Unit: */
159  struct timer *sh4_timer;
160  struct interrupt timer_irq[4];
161  uint32_t tocr;
162  uint32_t tstr;
163  uint32_t tcnt[N_SH4_TIMERS];
164  uint32_t tcor[N_SH4_TIMERS];
165  uint32_t tcr[N_SH4_TIMERS];
168 
169  /* RTC: */
170  uint32_t rtc_reg[14]; /* Excluding rcr1 and rcr2 */
171  uint8_t rtc_rcr1;
172  uint8_t rtc_rcr2;
173 };
174 
175 
176 #define SH4_PSEUDO_TIMER_HZ 110.0
177 
178 
179 /*
180  * sh4_timer_tick():
181  *
182  * This function is called SH4_PSEUDO_TIMER_HZ times per real-world second.
183  * Its job is to update the SH4 timer counters, and if necessary, increase
184  * the number of pending interrupts.
185  *
186  * Also, RAM Refresh is also faked here.
187  */
188 static void sh4_timer_tick(struct timer *t, void *extra)
189 {
190  struct sh4_data *d = (struct sh4_data *) extra;
191  int i;
192 
193  /* Fake RAM refresh: */
194  d->bsc_rfcr ++;
195  if (d->bsc_rtcsr & (RTCSR_CMIE | RTCSR_OVIE)) {
196  fatal("sh4: RTCSR_CMIE | RTCSR_OVIE: TODO\n");
197  /* TODO: Implement refresh interrupts etc. */
198  exit(1);
199  }
200 
201  /* Timer interrupts: */
202  for (i=0; i<N_SH4_TIMERS; i++) {
203  int32_t old = d->tcnt[i];
204 
205  /* printf("tcnt[%i] = %08x tcor[%i] = %08x\n",
206  i, d->tcnt[i], i, d->tcor[i]); */
207 
208  /* Only update timers that are currently started: */
209  if (!(d->tstr & (TSTR_STR0 << i)))
210  continue;
211 
212  /* Update the current count: */
213  d->tcnt[i] -= (uint32_t) (d->timer_hz[i] / SH4_PSEUDO_TIMER_HZ);
214 
215  /* Has the timer underflowed? */
216  if ((int32_t)d->tcnt[i] < 0 && old >= 0) {
217  d->tcr[i] |= TCR_UNF;
218 
219  if (d->tcr[i] & TCR_UNIE)
220  d->timer_interrupts_pending[i] ++;
221 
222  /*
223  * Set tcnt[i] to tcor[i]. Note: Since this function
224  * is only called now and then, adding tcor[i] to
225  * tcnt[i] produces more correct values for long
226  * running timers.
227  */
228  d->tcnt[i] += d->tcor[i];
229 
230  /* At least make sure that tcnt is non-negative... */
231  if ((int32_t)d->tcnt[i] < 0)
232  d->tcnt[i] = 0;
233  }
234  }
235 }
236 
237 
238 static void sh4_pcic_interrupt_assert(struct interrupt *interrupt)
239 {
240  struct sh4_data *d = (struct sh4_data *) interrupt->extra;
242 }
243 static void sh4_pcic_interrupt_deassert(struct interrupt *interrupt)
244 {
245  struct sh4_data *d = (struct sh4_data *) interrupt->extra;
247 }
248 
249 
250 static void scif_reassert_interrupts(struct sh4_data *d)
251 {
252  int old_tx_asserted = d->scif_tx_irq_asserted;
253  int old_rx_asserted = d->scif_rx_irq_asserted;
254 
256  d->scif_scr & SCSCR2_RIE && d->scif_ssr & SCSSR2_DR;
257 
258  if (d->scif_rx_irq_asserted && !old_rx_asserted)
260  else if (!d->scif_rx_irq_asserted && old_rx_asserted)
262 
264  d->scif_scr & SCSCR2_TIE &&
266 
267  if (d->scif_tx_irq_asserted && !old_tx_asserted)
269  else if (!d->scif_tx_irq_asserted && old_tx_asserted)
271 }
272 
273 
275 {
276  struct sh4_data *d = (struct sh4_data *) extra;
277  unsigned int i;
278 
279  /*
280  * Serial controller interrupts:
281  *
282  * RX: Cause interrupt if any char is available.
283  * TX: Send entire TX FIFO contents, and interrupt.
284  */
286  d->scif_ssr |= SCSSR2_DR;
287  else
288  d->scif_ssr &= ~SCSSR2_DR;
289 
290  if (d->scif_delayed_tx) {
291  if (--d->scif_delayed_tx == 0) {
292  /* Send TX FIFO contents: */
293  for (i=0; i<d->scif_tx_fifo_cursize; i++)
295  d->scif_tx_fifo[i]);
296 
297  /* Clear FIFO: */
298  d->scif_tx_fifo_cursize = 0;
299 
300  /* Done sending; cause a transmit end interrupt: */
302  }
303  }
304 
305  scif_reassert_interrupts(d);
306 
307  /* Timer interrupts: */
308  for (i=0; i<N_SH4_TIMERS; i++)
309  if (d->timer_interrupts_pending[i] > 0) {
311  d->tcr[i] |= TCR_UNF;
312  }
313 }
314 
315 
316 /*
317  * sh4_dmac_transfer():
318  *
319  * Called whenever a DMA transfer is to be executed.
320  * Clears the lowest bit of the corresponding channel's CHCR when done.
321  */
322 void sh4_dmac_transfer(struct cpu *cpu, struct sh4_data *d, int channel)
323 {
324  /* According to the SH7760 manual, bits 31..29 are ignored in */
325  /* both the SAR and DAR. */
326  uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
327  uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
328  uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
329  uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
330  int transmit_size = 1;
331  int src_delta = 0, dst_delta = 0;
332  int cause_interrupt = chcr & CHCR_IE;
333 
334  /* DMAC not enabled? Then just return. */
335  if (!(chcr & CHCR_TD))
336  return;
337 
338  /* Transfer End already set? Then don't transfer again. */
339  if (chcr & CHCR_TE)
340  return;
341 
342  /* Special case: 0 means 16777216: */
343  if (count == 0)
344  count = 16777216;
345 
346  switch (chcr & CHCR_TS) {
347  case CHCR_TS_8BYTE: transmit_size = 8; break;
348  case CHCR_TS_1BYTE: transmit_size = 1; break;
349  case CHCR_TS_2BYTE: transmit_size = 2; break;
350  case CHCR_TS_4BYTE: transmit_size = 4; break;
351  case CHCR_TS_32BYTE: transmit_size = 32; break;
352  default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
353  channel, chcr);
354  exit(1);
355  }
356 
357  switch (chcr & CHCR_DM) {
358  case CHCR_DM_FIXED: dst_delta = 0; break;
359  case CHCR_DM_INCREMENTED: dst_delta = 1; break;
360  case CHCR_DM_DECREMENTED: dst_delta = -1; break;
361  default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
362  channel, chcr);
363  exit(1);
364  }
365 
366  switch (chcr & CHCR_SM) {
367  case CHCR_SM_FIXED: src_delta = 0; break;
368  case CHCR_SM_INCREMENTED: src_delta = 1; break;
369  case CHCR_SM_DECREMENTED: src_delta = -1; break;
370  default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
371  channel, chcr);
372  exit(1);
373  }
374 
375  src_delta *= transmit_size;
376  dst_delta *= transmit_size;
377 
378 #ifdef SH4_DEBUG
379  fatal("|SH4 DMA transfer, channel %i\n", channel);
380  fatal("|Source addr: 0x%08x (delta %i)\n", (int) sar, src_delta);
381  fatal("|Destination addr: 0x%08x (delta %i)\n", (int) dar, dst_delta);
382  fatal("|Count: 0x%08x\n", (int) count);
383  fatal("|Transmit size: 0x%08x\n", (int) transmit_size);
384  fatal("|Interrupt: %s\n", cause_interrupt? "yes" : "no");
385 #endif
386 
387  switch (chcr & CHCR_RS) {
388  case 0x200:
389  /*
390  * Single Address Mode
391  * External Address Space => external device
392  */
393 
394  // Avoid compiler warnings about unused sar and dar.
395  (void)sar;
396  (void)dar;
397 
398  /* Note: No transfer is done here! It is up to the
399  external device to do the transfer itself! */
400  break;
401 
402  default:fatal("Unimplemented SH4 RS DMAC: 0x%08x\n",
403  (int) (chcr & CHCR_RS));
404  exit(1);
405  }
406 
407  if (cause_interrupt) {
408  fatal("TODO: sh4 dmac interrupt!\n");
409  exit(1);
410  }
411 }
412 
413 
414 /*
415  * sh4_sci_cmd():
416  *
417  * Handle a SCI command byte.
418  *
419  * Bit: Meaning:
420  * 7 Ignored (usually 1?)
421  * 6 0=Write, 1=Read
422  * 5 AD: Address transfer
423  * 4 DT: Data transfer
424  * 3..0 Data or address bits
425  */
426 static void sh4_sci_cmd(struct sh4_data *d, struct cpu *cpu)
427 {
428  uint8_t cmd = d->sci_curbyte;
429  int writeflag = cmd & 0x40? 0 : 1;
430  int address_transfer;
431 
432  /* fatal("[ CMD BYTE %02x ]\n", cmd); */
433 
434  if (!(cmd & 0x80)) {
435  fatal("SCI cmd bit 7 not set? TODO\n");
436  exit(1);
437  }
438 
439  if ((cmd & 0x30) == 0x20)
440  address_transfer = 1;
441  else if ((cmd & 0x30) == 0x10)
442  address_transfer = 0;
443  else {
444  fatal("SCI: Neither data nor address transfer? TODO\n");
445  exit(1);
446  }
447 
448  if (address_transfer)
449  d->sci_cur_addr = cmd & 0x0f;
450 
451  if (!writeflag) {
452  /* Read data from the current address: */
453  uint8_t data_byte;
454 
456  &data_byte, 1, MEM_READ, PHYSICAL);
457 
458  debug("[ SCI: read addr=%x data=%x ]\n",
459  d->sci_cur_addr, data_byte);
460 
461  d->sci_curbyte = data_byte;
462 
463  /* Set bit 7 right away: */
464  d->sci_scsptr &= ~SCSPTR_SPB1DT;
465  if (data_byte & 0x80)
467  }
468 
469  if (writeflag && !address_transfer) {
470  /* Write the 4 data bits to the current address: */
471  uint8_t data_byte = cmd & 0x0f;
472 
473  debug("[ SCI: write addr=%x data=%x ]\n",
474  d->sci_cur_addr, data_byte);
475 
477  &data_byte, 1, MEM_WRITE, PHYSICAL);
478  }
479 }
480 
481 
482 /*
483  * sh4_sci_access():
484  *
485  * Reads or writes a bit via the SH4's serial interface. If writeflag is
486  * non-zero, input is used. If writeflag is zero, a bit is outputed as
487  * the return value from this function.
488  */
489 static uint8_t sh4_sci_access(struct sh4_data *d, struct cpu *cpu,
490  int writeflag, uint8_t input)
491 {
492  if (writeflag) {
493  /* WRITE: */
494  int clockpulse;
495  uint8_t old = d->sci_scsptr;
496  d->sci_scsptr = input;
497 
498  /*
499  * Clock pulse (SCSPTR_SPB0DT going from 0 to 1,
500  * when SCSPTR_SPB0IO was already set):
501  */
502  clockpulse = old & SCSPTR_SPB0IO &&
503  d->sci_scsptr & SCSPTR_SPB0DT &&
504  !(old & SCSPTR_SPB0DT);
505 
506  if (!clockpulse)
507  return 0;
508 
509  /* Are we in output or input mode? */
510  if (d->sci_scsptr & SCSPTR_SPB1IO) {
511  /* Output: */
512  int bit = d->sci_scsptr & SCSPTR_SPB1DT? 1 : 0;
513  d->sci_curbyte <<= 1;
514  d->sci_curbyte |= bit;
515  d->sci_bits_outputed ++;
516  if (d->sci_bits_outputed == 8) {
517  /* 4 control bits and 4 address/data bits have
518  been written. */
519  sh4_sci_cmd(d, cpu);
520  d->sci_bits_outputed = 0;
521  }
522  } else {
523  /* Input: */
524  int bit;
525  d->sci_bits_read ++;
526  d->sci_bits_read &= 7;
527 
528  bit = d->sci_curbyte & (0x80 >> d->sci_bits_read);
529 
530  d->sci_scsptr &= ~SCSPTR_SPB1DT;
531  if (bit)
533  }
534 
535  /* Return (value doesn't matter). */
536  return 0;
537  } else {
538  /* READ: */
539  return d->sci_scsptr;
540  }
541 }
542 
543 
544 DEVICE_ACCESS(sh4_itlb_aa)
545 {
546  uint64_t idata = 0, odata = 0;
547  int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
548 
549  if (writeflag == MEM_WRITE) {
550  int safe_to_invalidate = 0;
551  uint32_t old_hi = cpu->cd.sh.itlb_hi[e];
553  safe_to_invalidate = 1;
554 
555  idata = memory_readmax64(cpu, data, len);
556  cpu->cd.sh.itlb_hi[e] &=
558  cpu->cd.sh.itlb_hi[e] |= (idata &
560  cpu->cd.sh.itlb_lo[e] &= ~SH4_PTEL_V;
561  if (idata & SH4_ITLB_AA_V)
562  cpu->cd.sh.itlb_lo[e] |= SH4_PTEL_V;
563 
564  /* Invalidate if this ITLB entry previously belonged to the
565  currently running process, or if it was shared: */
566  if (cpu->cd.sh.ptel & SH4_PTEL_SH ||
567  (old_hi & SH4_ITLB_AA_ASID_MASK) ==
569  if (safe_to_invalidate)
571  old_hi & ~0xfff, INVALIDATE_VADDR);
572  else
574  0, INVALIDATE_ALL);
575  }
576  } else {
577  odata = cpu->cd.sh.itlb_hi[e] &
579  if (cpu->cd.sh.itlb_lo[e] & SH4_PTEL_V)
580  odata |= SH4_ITLB_AA_V;
581  memory_writemax64(cpu, data, len, odata);
582  }
583 
584  return 1;
585 }
586 
587 
588 DEVICE_ACCESS(sh4_itlb_da1)
589 {
590  uint32_t mask = SH4_PTEL_SH | SH4_PTEL_C | SH4_PTEL_SZ_MASK |
591  SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
592  uint64_t idata = 0, odata = 0;
593  int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
594 
595  if (relative_addr & 0x800000) {
596  fatal("sh4_itlb_da1: TODO: da2 area\n");
597  exit(1);
598  }
599 
600  if (writeflag == MEM_WRITE) {
601  uint32_t old_lo = cpu->cd.sh.itlb_lo[e];
602  int safe_to_invalidate = 0;
604  safe_to_invalidate = 1;
605 
606  idata = memory_readmax64(cpu, data, len);
607  cpu->cd.sh.itlb_lo[e] &= ~mask;
608  cpu->cd.sh.itlb_lo[e] |= (idata & mask);
609 
610  /* Invalidate if this ITLB entry belongs to the
611  currently running process, or if it was shared: */
612  if (old_lo & SH4_PTEL_SH ||
615  if (safe_to_invalidate)
617  cpu->cd.sh.itlb_hi[e] & ~0xfff,
619  else
621  0, INVALIDATE_ALL);
622  }
623  } else {
624  odata = cpu->cd.sh.itlb_lo[e] & mask;
625  memory_writemax64(cpu, data, len, odata);
626  }
627 
628  return 1;
629 }
630 
631 
632 DEVICE_ACCESS(sh4_utlb_aa)
633 {
634  uint64_t idata = 0, odata = 0;
635  int i, e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
636  int a = relative_addr & SH4_UTLB_A;
637 
638  if (writeflag == MEM_WRITE) {
639  int n_hits = 0;
640  int safe_to_invalidate = 0;
641  uint32_t vaddr_to_invalidate = 0;
642 
643  idata = memory_readmax64(cpu, data, len);
644  if (a) {
645  for (i=-SH_N_ITLB_ENTRIES; i<SH_N_UTLB_ENTRIES; i++) {
646  uint32_t lo, hi;
647  uint32_t mask = 0xfffff000;
648  int sh;
649 
650  if (i < 0) {
651  lo = cpu->cd.sh.itlb_lo[
652  i + SH_N_ITLB_ENTRIES];
653  hi = cpu->cd.sh.itlb_hi[
654  i + SH_N_ITLB_ENTRIES];
655  } else {
656  lo = cpu->cd.sh.utlb_lo[i];
657  hi = cpu->cd.sh.utlb_hi[i];
658  }
659 
660  sh = lo & SH4_PTEL_SH;
661  if (!(lo & SH4_PTEL_V))
662  continue;
663 
664  switch (lo & SH4_PTEL_SZ_MASK) {
665  case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break;
666  case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
667  case SH4_PTEL_SZ_1M: mask = 0xfff00000; break;
668  }
669 
670  if ((hi & mask) != (idata & mask))
671  continue;
672 
673  if ((lo & SH4_PTEL_SZ_MASK) ==
674  SH4_PTEL_SZ_4K) {
675  safe_to_invalidate = 1;
676  vaddr_to_invalidate = hi & mask;
677  }
678 
679  if (!sh && (hi & SH4_PTEH_ASID_MASK) !=
681  continue;
682 
683  if (i < 0) {
684  cpu->cd.sh.itlb_lo[i +
686  if (idata & SH4_UTLB_AA_V)
687  cpu->cd.sh.itlb_lo[
688  i+SH_N_ITLB_ENTRIES] |=
689  SH4_PTEL_V;
690  } else {
691  cpu->cd.sh.utlb_lo[i] &=
692  ~(SH4_PTEL_D | SH4_PTEL_V);
693  if (idata & SH4_UTLB_AA_D)
694  cpu->cd.sh.utlb_lo[i] |=
695  SH4_PTEL_D;
696  if (idata & SH4_UTLB_AA_V)
697  cpu->cd.sh.utlb_lo[i] |=
698  SH4_PTEL_V;
699  }
700 
701  if (i >= 0)
702  n_hits ++;
703  }
704 
705  if (n_hits > 1)
708  } else {
709  if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK) ==
710  SH4_PTEL_SZ_4K) {
711  safe_to_invalidate = 1;
712  vaddr_to_invalidate =
713  cpu->cd.sh.utlb_hi[e] & ~0xfff;
714  }
715 
716  cpu->cd.sh.utlb_hi[e] &=
718  cpu->cd.sh.utlb_hi[e] |= (idata &
720 
721  cpu->cd.sh.utlb_lo[e] &= ~(SH4_PTEL_D | SH4_PTEL_V);
722  if (idata & SH4_UTLB_AA_D)
723  cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_D;
724  if (idata & SH4_UTLB_AA_V)
725  cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_V;
726  }
727 
728  if (safe_to_invalidate)
730  vaddr_to_invalidate, INVALIDATE_VADDR);
731  else
734  } else {
735  odata = cpu->cd.sh.utlb_hi[e] &
737  if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_D)
738  odata |= SH4_UTLB_AA_D;
739  if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_V)
740  odata |= SH4_UTLB_AA_V;
741  memory_writemax64(cpu, data, len, odata);
742  }
743 
744  return 1;
745 }
746 
747 
748 DEVICE_ACCESS(sh4_utlb_da1)
749 {
750  uint32_t mask = SH4_PTEL_WT | SH4_PTEL_SH | SH4_PTEL_D | SH4_PTEL_C
751  | SH4_PTEL_SZ_MASK | SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
752  uint64_t idata = 0, odata = 0;
753  int e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
754 
755  if (relative_addr & 0x800000) {
756  fatal("sh4_utlb_da1: TODO: da2 area\n");
757  exit(1);
758  }
759 
760  if (writeflag == MEM_WRITE) {
761  uint32_t old_lo = cpu->cd.sh.utlb_lo[e];
762  int safe_to_invalidate = 0;
764  safe_to_invalidate = 1;
765 
766  idata = memory_readmax64(cpu, data, len);
767  cpu->cd.sh.utlb_lo[e] &= ~mask;
768  cpu->cd.sh.utlb_lo[e] |= (idata & mask);
769 
770  /* Invalidate if this UTLB entry belongs to the
771  currently running process, or if it was shared: */
772  if (old_lo & SH4_PTEL_SH ||
775  if (safe_to_invalidate)
777  cpu->cd.sh.utlb_hi[e] & ~0xfff,
779  else
781  0, INVALIDATE_ALL);
782  }
783  } else {
784  odata = cpu->cd.sh.utlb_lo[e] & mask;
785  memory_writemax64(cpu, data, len, odata);
786  }
787 
788  return 1;
789 }
790 
791 
792 DEVICE_ACCESS(sh4_pcic)
793 {
794  struct sh4_data *d = (struct sh4_data *) extra;
795  uint64_t idata = 0, odata = 0;
796 
797  if (writeflag == MEM_WRITE)
798  idata = memory_readmax64(cpu, data, len);
799 
800  relative_addr += SH4_PCIC;
801 
802  /* Register read/write: */
803  if (writeflag == MEM_WRITE)
804  d->pcic_reg[PCIC_REG(relative_addr)] = idata;
805  else
806  odata = d->pcic_reg[PCIC_REG(relative_addr)];
807 
808  /* Special cases: */
809 
810  switch (relative_addr) {
811 
812  case SH4_PCICONF0:
813  if (writeflag == MEM_WRITE) {
814  fatal("[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n");
815  exit(1);
816  } else {
817  if (strcmp(cpu->cd.sh.cpu_type.name, "SH7751") == 0) {
820  } else if (strcmp(cpu->cd.sh.cpu_type.name,
821  "SH7751R") == 0) {
824  } else {
825  fatal("sh4_pcic: TODO: PCICONF0 read for"
826  " unimplemented CPU type?\n");
827  exit(1);
828  }
829  }
830  break;
831 
832  case SH4_PCICONF1:
833  case SH4_PCICONF2:
834  case SH4_PCICR:
835  case SH4_PCIBCR1:
836  case SH4_PCIBCR2:
837  case SH4_PCIBCR3:
838  case SH4_PCIWCR1:
839  case SH4_PCIWCR2:
840  case SH4_PCIWCR3:
841  case SH4_PCIMCR:
842  break;
843 
844  case SH4_PCICONF5:
845  /* Hardcoded to what OpenBSD/landisk uses: */
846  if (writeflag == MEM_WRITE && idata != 0xac000000) {
847  fatal("sh4_pcic: SH4_PCICONF5 unknown value"
848  " 0x%" PRIx32"\n", (uint32_t) idata);
849  exit(1);
850  }
851  break;
852 
853  case SH4_PCICONF6:
854  /* Hardcoded to what OpenBSD/landisk uses: */
855  if (writeflag == MEM_WRITE && idata != 0x8c000000) {
856  fatal("sh4_pcic: SH4_PCICONF6 unknown value"
857  " 0x%" PRIx32"\n", (uint32_t) idata);
858  exit(1);
859  }
860  break;
861 
862  case SH4_PCILSR0:
863  /* Hardcoded to what OpenBSD/landisk uses: */
864  if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
865  fatal("sh4_pcic: SH4_PCILSR0 unknown value"
866  " 0x%" PRIx32"\n", (uint32_t) idata);
867  exit(1);
868  }
869  break;
870 
871  case SH4_PCILAR0:
872  /* Hardcoded to what OpenBSD/landisk uses: */
873  if (writeflag == MEM_WRITE && idata != 0xac000000) {
874  fatal("sh4_pcic: SH4_PCILAR0 unknown value"
875  " 0x%" PRIx32"\n", (uint32_t) idata);
876  exit(1);
877  }
878  break;
879 
880  case SH4_PCILSR1:
881  /* Hardcoded to what OpenBSD/landisk uses: */
882  if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
883  fatal("sh4_pcic: SH4_PCILSR1 unknown value"
884  " 0x%" PRIx32"\n", (uint32_t) idata);
885  exit(1);
886  }
887  break;
888 
889  case SH4_PCILAR1:
890  /* Hardcoded to what OpenBSD/landisk uses: */
891  if (writeflag == MEM_WRITE && idata != 0xac000000) {
892  fatal("sh4_pcic: SH4_PCILAR1 unknown value"
893  " 0x%" PRIx32"\n", (uint32_t) idata);
894  exit(1);
895  }
896  break;
897 
898  case SH4_PCIMBR:
899  if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) {
900  fatal("sh4_pcic: PCIMBR set to 0x%" PRIx32", not"
901  " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
902  (uint32_t) SH4_PCIC_MEM);
903  exit(1);
904  }
905  break;
906 
907  case SH4_PCIIOBR:
908  if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) {
909  fatal("sh4_pcic: PCIIOBR set to 0x%" PRIx32", not"
910  " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
911  (uint32_t) SH4_PCIC_IO);
912  exit(1);
913  }
914  break;
915 
916  case SH4_PCIPAR:
917  /* PCI bus access Address Register: */
918  {
919  int bus = (idata >> 16) & 0xff;
920  int dev = (idata >> 11) & 0x1f;
921  int func = (idata >> 8) & 7;
922  int reg = idata & 0xff;
923  bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
924  }
925  break;
926 
927  case SH4_PCIPDR:
928  /* PCI bus access Data Register: */
929  bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
930  &odata : &idata, len, writeflag);
931  break;
932 
933  default:if (writeflag == MEM_READ) {
934  fatal("[ sh4_pcic: read from addr 0x%x: TODO ]\n",
935  (int)relative_addr);
936  } else {
937  fatal("[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n",
938  (int)relative_addr, (int)idata);
939  }
940  exit(1);
941  }
942 
943  if (writeflag == MEM_READ)
944  memory_writemax64(cpu, data, len, odata);
945 
946  return 1;
947 }
948 
949 
951 {
952  struct sh4_data *d = (struct sh4_data *) extra;
953  size_t i;
954 
955  if (writeflag == MEM_WRITE) {
956  for (i=0; i<len; i++)
957  d->sq[(relative_addr + i) % sizeof(d->sq)] = data[i];
958  } else {
959  for (i=0; i<len; i++)
960  data[i] = d->sq[(relative_addr + i) % sizeof(d->sq)];
961  }
962 
963  return 1;
964 }
965 
966 
968 {
969  struct sh4_data *d = (struct sh4_data *) extra;
970  uint64_t idata = 0, odata = 0;
971  int timer_nr = 0, dma_channel = 0;
972 
973  if (writeflag == MEM_WRITE)
974  idata = memory_readmax64(cpu, data, len);
975 
976  relative_addr += SH4_REG_BASE;
977 
978  /* SD-RAM access uses address only: */
979  if (relative_addr >= 0xff900000 && relative_addr <= 0xff97ffff) {
980  /* Possibly not 100% correct... TODO */
981  int v = (relative_addr >> 2) & 0xffff;
982  if (relative_addr & 0x00040000)
983  d->sdmr3 = v;
984  else
985  d->sdmr2 = v;
986  debug("[ sh4: sdmr%i set to 0x%04" PRIx16" ]\n",
987  relative_addr & 0x00040000? 3 : 2, v);
988  return 1;
989  }
990 
991 
992  switch (relative_addr) {
993 
994  /*************************************************/
995 
996  case SH4_PVR_ADDR:
997  odata = cpu->cd.sh.cpu_type.pvr;
998  break;
999 
1000  case SH4_PRR_ADDR:
1001  odata = cpu->cd.sh.cpu_type.prr;
1002  break;
1003 
1004  case SH4_PTEH:
1005  if (writeflag == MEM_READ)
1006  odata = cpu->cd.sh.pteh;
1007  else {
1008  unsigned int old_asid = cpu->cd.sh.pteh
1010  cpu->cd.sh.pteh = idata;
1011 
1012  if ((idata & SH4_PTEH_ASID_MASK) != old_asid) {
1013  /*
1014  * TODO: Don't invalidate everything,
1015  * only those pages that belonged to the
1016  * old asid.
1017  */
1019  cpu, 0, INVALIDATE_ALL);
1020  }
1021  }
1022  break;
1023 
1024  case SH4_PTEL:
1025  if (writeflag == MEM_READ)
1026  odata = cpu->cd.sh.ptel;
1027  else
1028  cpu->cd.sh.ptel = idata;
1029  break;
1030 
1031  case SH4_TTB:
1032  if (writeflag == MEM_READ)
1033  odata = cpu->cd.sh.ttb;
1034  else
1035  cpu->cd.sh.ttb = idata;
1036  break;
1037 
1038  case SH4_TEA:
1039  if (writeflag == MEM_READ)
1040  odata = cpu->cd.sh.tea;
1041  else
1042  cpu->cd.sh.tea = idata;
1043  break;
1044 
1045  case SH4_PTEA:
1046  if (writeflag == MEM_READ)
1047  odata = cpu->cd.sh.ptea;
1048  else
1049  cpu->cd.sh.ptea = idata;
1050  break;
1051 
1052  case SH4_MMUCR:
1053  if (writeflag == MEM_READ) {
1054  odata = cpu->cd.sh.mmucr;
1055  } else {
1056  if (idata & SH4_MMUCR_TI) {
1057  /* TLB invalidate. */
1058  int i;
1059  for (i = 0; i < SH_N_ITLB_ENTRIES; i++)
1060  cpu->cd.sh.itlb_lo[i] &=
1061  ~SH4_PTEL_V;
1062 
1063  for (i = 0; i < SH_N_UTLB_ENTRIES; i++)
1064  cpu->cd.sh.utlb_lo[i] &=
1065  ~SH4_PTEL_V;
1066 
1068  0, INVALIDATE_ALL);
1069 
1070  /* The TI bit should always read as 0. */
1071  idata &= ~SH4_MMUCR_TI;
1072  }
1073 
1074  cpu->cd.sh.mmucr = idata;
1075  }
1076  break;
1077 
1078  case SH4_CCR:
1079  if (writeflag == MEM_READ) {
1080  odata = cpu->cd.sh.ccr;
1081  } else {
1082  cpu->cd.sh.ccr = idata;
1083  }
1084  break;
1085 
1086  case SH4_QACR0:
1087  if (writeflag == MEM_READ) {
1088  odata = cpu->cd.sh.qacr0;
1089  } else {
1090  cpu->cd.sh.qacr0 = idata;
1091  }
1092  break;
1093 
1094  case SH4_QACR1:
1095  if (writeflag == MEM_READ) {
1096  odata = cpu->cd.sh.qacr1;
1097  } else {
1098  cpu->cd.sh.qacr1 = idata;
1099  }
1100  break;
1101 
1102  case SH4_TRA:
1103  if (writeflag == MEM_READ)
1104  odata = cpu->cd.sh.tra;
1105  else
1106  cpu->cd.sh.tra = idata;
1107  break;
1108 
1109  case SH4_EXPEVT:
1110  if (writeflag == MEM_READ)
1111  odata = cpu->cd.sh.expevt;
1112  else
1113  cpu->cd.sh.expevt = idata;
1114  break;
1115 
1116  case SH4_INTEVT:
1117  if (writeflag == MEM_READ)
1118  odata = cpu->cd.sh.intevt;
1119  else
1120  cpu->cd.sh.intevt = idata;
1121  break;
1122 
1123 
1124  /********************************/
1125  /* UBC: User Break Controller */
1126 
1127  case 0xff000014: /* SH4_UBC_BASRA */
1128  case 0xff000018: /* SH4_UBC_BASRB */
1129 
1130  case 0xff200000: /* SH4_UBC_BARA */
1131  case 0xff200004: /* SH4_UBC_BAMRA */
1132  case 0xff200008: /* SH4_UBC_BBRA */
1133  case 0xff20000c: /* SH4_UBC_BARB */
1134  case 0xff200010: /* SH4_UBC_BAMRB */
1135  case 0xff200014: /* SH4_UBC_BBRB */
1136  case 0xff200018: /* SH4_UBC_BDRB */
1137  case 0xff20001c: /* SH4_UBC_BDMRB */
1138  case 0xff200020: /* SH4_UBC_BRCR */
1139  /* TODO */
1140  break;
1141 
1142 
1143  /********************************/
1144  /* TMU: Timer Management Unit */
1145 
1146  case SH4_TOCR:
1147  /* Timer Output Control Register */
1148  if (writeflag == MEM_WRITE) {
1149  d->tocr = idata;
1150  if (idata & TOCR_TCOE)
1151  fatal("[ sh4 timer: TCOE not yet "
1152  "implemented ]\n");
1153  } else {
1154  odata = d->tocr;
1155  }
1156  break;
1157 
1158  case SH4_TSTR:
1159  /* Timer Start Register */
1160  if (writeflag == MEM_READ) {
1161  odata = d->tstr;
1162  } else {
1163  if (idata & 1 && !(d->tstr & 1))
1164  debug("[ sh4 timer: starting timer 0 ]\n");
1165  if (idata & 2 && !(d->tstr & 2))
1166  debug("[ sh4 timer: starting timer 1 ]\n");
1167  if (idata & 4 && !(d->tstr & 4))
1168  debug("[ sh4 timer: starting timer 2 ]\n");
1169  if (!(idata & 1) && d->tstr & 1)
1170  debug("[ sh4 timer: stopping timer 0 ]\n");
1171  if (!(idata & 2) && d->tstr & 2)
1172  debug("[ sh4 timer: stopping timer 1 ]\n");
1173  if (!(idata & 4) && d->tstr & 4)
1174  debug("[ sh4 timer: stopping timer 2 ]\n");
1175  d->tstr = idata;
1176  }
1177  break;
1178 
1179  case SH4_TCOR2:
1180  timer_nr ++;
1181  case SH4_TCOR1:
1182  timer_nr ++;
1183  case SH4_TCOR0:
1184  /* Timer Constant Register */
1185  if (writeflag == MEM_READ)
1186  odata = d->tcor[timer_nr];
1187  else
1188  d->tcor[timer_nr] = idata;
1189  break;
1190 
1191  case SH4_TCNT2:
1192  timer_nr ++;
1193  case SH4_TCNT1:
1194  timer_nr ++;
1195  case SH4_TCNT0:
1196  /* Timer Counter Register */
1197  if (writeflag == MEM_READ)
1198  odata = d->tcnt[timer_nr];
1199  else
1200  d->tcnt[timer_nr] = idata;
1201  break;
1202 
1203  case SH4_TCR2:
1204  timer_nr ++;
1205  case SH4_TCR1:
1206  timer_nr ++;
1207  case SH4_TCR0:
1208  /* Timer Control Register */
1209  if (writeflag == MEM_READ) {
1210  odata = d->tcr[timer_nr];
1211  } else {
1212  if (cpu->cd.sh.pclock == 0) {
1213  fatal("INTERNAL ERROR: pclock must be set"
1214  " for this machine. Aborting.\n");
1215  exit(1);
1216  }
1217 
1218  switch (idata & 3) {
1219  case TCR_TPSC_P4:
1220  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/4.0;
1221  break;
1222  case TCR_TPSC_P16:
1223  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/16.0;
1224  break;
1225  case TCR_TPSC_P64:
1226  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/64.0;
1227  break;
1228  case TCR_TPSC_P256:
1229  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/256.0;
1230  break;
1231  }
1232 
1233  debug("[ sh4 timer %i clock set to %f Hz ]\n",
1234  timer_nr, d->timer_hz[timer_nr]);
1235 
1236  if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 |
1237  TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) {
1238  fatal("Unimplemented SH4 timer control"
1239  " bits: 0x%08" PRIx32". Aborting.\n",
1240  (int) idata);
1241  exit(1);
1242  }
1243 
1244  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
1245 
1246  if (d->tcr[timer_nr] & TCR_UNF && !(idata & TCR_UNF)) {
1247  if (d->timer_interrupts_pending[timer_nr] > 0)
1248  d->timer_interrupts_pending[timer_nr]--;
1249  }
1250 
1251  d->tcr[timer_nr] = idata;
1252  }
1253  break;
1254 
1255 
1256  /*************************************************/
1257  /* DMAC: DMA Controller */
1258  /* 4 channels on SH7750 */
1259  /* 8 channels on SH7760 */
1260 
1261  case SH4_SAR7: dma_channel ++;
1262  case SH4_SAR6: dma_channel ++;
1263  case SH4_SAR5: dma_channel ++;
1264  case SH4_SAR4: dma_channel ++;
1265  case SH4_SAR3: dma_channel ++;
1266  case SH4_SAR2: dma_channel ++;
1267  case SH4_SAR1: dma_channel ++;
1268  case SH4_SAR0:
1269  if (writeflag == MEM_READ)
1270  odata = cpu->cd.sh.dmac_sar[dma_channel];
1271  else
1272  cpu->cd.sh.dmac_sar[dma_channel] = idata;
1273  break;
1274 
1275  case SH4_DAR7: dma_channel ++;
1276  case SH4_DAR6: dma_channel ++;
1277  case SH4_DAR5: dma_channel ++;
1278  case SH4_DAR4: dma_channel ++;
1279  case SH4_DAR3: dma_channel ++;
1280  case SH4_DAR2: dma_channel ++;
1281  case SH4_DAR1: dma_channel ++;
1282  case SH4_DAR0:
1283  if (writeflag == MEM_READ)
1284  odata = cpu->cd.sh.dmac_dar[dma_channel];
1285  else
1286  cpu->cd.sh.dmac_dar[dma_channel] = idata;
1287  break;
1288 
1289  case SH4_DMATCR7: dma_channel ++;
1290  case SH4_DMATCR6: dma_channel ++;
1291  case SH4_DMATCR5: dma_channel ++;
1292  case SH4_DMATCR4: dma_channel ++;
1293  case SH4_DMATCR3: dma_channel ++;
1294  case SH4_DMATCR2: dma_channel ++;
1295  case SH4_DMATCR1: dma_channel ++;
1296  case SH4_DMATCR0:
1297  if (writeflag == MEM_READ)
1298  odata = cpu->cd.sh.dmac_tcr[dma_channel] & 0x00ffffff;
1299  else {
1300  if (idata & ~0x00ffffff) {
1301  fatal("[ SH4 DMA: Attempt to set top 8 "
1302  "bits of the count register? 0x%08"
1303  PRIx32" ]\n", (uint32_t) idata);
1304  exit(1);
1305  }
1306 
1307  cpu->cd.sh.dmac_tcr[dma_channel] = idata;
1308  }
1309  break;
1310 
1311  case SH4_CHCR7: dma_channel ++;
1312  case SH4_CHCR6: dma_channel ++;
1313  case SH4_CHCR5: dma_channel ++;
1314  case SH4_CHCR4: dma_channel ++;
1315  case SH4_CHCR3: dma_channel ++;
1316  case SH4_CHCR2: dma_channel ++;
1317  case SH4_CHCR1: dma_channel ++;
1318  case SH4_CHCR0:
1319  if (writeflag == MEM_READ) {
1320  odata = cpu->cd.sh.dmac_chcr[dma_channel];
1321  } else {
1322  /* CHCR_CHSET always reads back as 0: */
1323  idata &= ~CHCR_CHSET;
1324 
1325  cpu->cd.sh.dmac_chcr[dma_channel] = idata;
1326 
1327  /* Perform a transfer? */
1328  if (idata & CHCR_TD)
1329  sh4_dmac_transfer(cpu, d, dma_channel);
1330  }
1331  break;
1332 
1333  case SH4_DMAOR:
1334  if (writeflag == MEM_READ) {
1335  odata = cpu->cd.sh.dmaor;
1336  } else {
1337  // Only some bits are writable:
1338  idata &= (DMAOR_DDT | DMAOR_PR1 | DMAOR_PR0 | DMAOR_DME);
1339  cpu->cd.sh.dmaor = idata;
1340  }
1341  break;
1342 
1343  /*************************************************/
1344  /* BSC: Bus State Controller */
1345 
1346  case SH4_BCR1:
1347  if (writeflag == MEM_WRITE)
1348  d->bsc_bcr1 = idata & 0x033efffd;
1349  else {
1350  odata = d->bsc_bcr1;
1352  odata |= BCR1_LITTLE_ENDIAN;
1353  }
1354  break;
1355 
1356  case SH4_BCR2:
1357  if (len != sizeof(uint16_t)) {
1358  fatal("Non-16-bit SH4_BCR2 access?\n");
1359  exit(1);
1360  }
1361  if (writeflag == MEM_WRITE)
1362  d->bsc_bcr2 = idata & 0x3ffd;
1363  else
1364  odata = d->bsc_bcr2;
1365  break;
1366 
1367  case SH4_BCR3:
1368  if (len != sizeof(uint16_t)) {
1369  fatal("Non-16-bit SH4_BCR3 access?\n");
1370  exit(1);
1371  }
1372  if (writeflag == MEM_WRITE)
1373  d->bsc_bcr3 = idata;
1374  else
1375  odata = d->bsc_bcr3;
1376  break;
1377 
1378  case SH4_WCR1:
1379  if (writeflag == MEM_WRITE)
1380  d->bsc_wcr1 = idata & 0x77777777;
1381  else
1382  odata = d->bsc_wcr1;
1383  break;
1384 
1385  case SH4_WCR2:
1386  if (writeflag == MEM_WRITE)
1387  d->bsc_wcr2 = idata & 0xfffeefff;
1388  else
1389  odata = d->bsc_wcr2;
1390  break;
1391 
1392  case SH4_WCR3:
1393  if (writeflag == MEM_WRITE)
1394  d->bsc_wcr3 = idata & 0x77777777;
1395  else
1396  odata = d->bsc_wcr3;
1397  break;
1398 
1399  case SH4_MCR:
1400  if (writeflag == MEM_WRITE)
1401  d->bsc_mcr = idata & 0xf8bbffff;
1402  else
1403  odata = d->bsc_mcr;
1404  break;
1405 
1406  case SH4_PCR:
1407  if (writeflag == MEM_WRITE)
1408  d->bsc_pcr = idata;
1409  else
1410  odata = d->bsc_pcr;
1411  break;
1412 
1413  case SH4_RTCSR:
1414  /*
1415  * Refresh Time Control/Status Register. Called RTCSR in
1416  * NetBSD, but RTSCR in the SH7750 manual?
1417  */
1418  if (writeflag == MEM_WRITE) {
1419  idata &= 0x00ff;
1420  if (idata & RTCSR_CMF) {
1421  idata = (idata & ~RTCSR_CMF)
1422  | (d->bsc_rtcsr & RTCSR_CMF);
1423  }
1424  d->bsc_rtcsr = idata & 0x00ff;
1425  } else
1426  odata = d->bsc_rtcsr;
1427  break;
1428 
1429  case SH4_RTCOR:
1430  /* Refresh Time Constant Register (8 bits): */
1431  if (writeflag == MEM_WRITE)
1432  d->bsc_rtcor = idata & 0x00ff;
1433  else
1434  odata = d->bsc_rtcor & 0x00ff;
1435  break;
1436 
1437  case SH4_RFCR:
1438  /* Refresh Count Register (10 bits): */
1439  if (writeflag == MEM_WRITE)
1440  d->bsc_rfcr = idata & 0x03ff;
1441  else
1442  odata = d->bsc_rfcr & 0x03ff;
1443  break;
1444 
1445 
1446  /*******************************************/
1447  /* GPIO: General-purpose I/O controller */
1448 
1449  case SH4_PCTRA:
1450  if (writeflag == MEM_WRITE) {
1451  d->pctra = idata;
1452 
1453  // Hack: Makes the Dreamcast BIOS pass "cable select"
1454  // detection, it seems, without hanging in an endless
1455  // loop.
1456  d->pdtra |= 0x03;
1457  } else {
1458  odata = d->pctra;
1459  }
1460  break;
1461 
1462  case SH4_PDTRA:
1463  if (writeflag == MEM_WRITE) {
1464  // debug("[ sh4: pdtra: write 0x%08x (while pctra = 0x%08x) ]\n", (int)idata, (int)d->pctra);
1465  d->pdtra = idata;
1466 
1467  // Hack: Makes the Dreamcast BIOS pass "cable select"
1468  // detection, it seems, without hanging in an endless
1469  // loop.
1470  if ((idata & 1) == 0 || (idata & 2) == 0)
1471  d->pdtra &= ~3;
1472  } else {
1473  // debug("[ sh4: pdtra: read ]\n");
1474  odata = d->pdtra;
1475 
1476  // bits 8..9 on Dreamcast mean:
1477  // 00 = VGA, 10 = RGB, 11 = composite.
1478  odata |= (0 << 8);
1479  }
1480  break;
1481 
1482  case SH4_PCTRB:
1483  if (writeflag == MEM_WRITE)
1484  d->pctrb = idata;
1485  else
1486  odata = d->pctrb;
1487  break;
1488 
1489  case SH4_PDTRB:
1490  if (writeflag == MEM_WRITE) {
1491  debug("[ sh4: pdtrb: write: TODO ]\n");
1492  d->pdtrb = idata;
1493  } else {
1494  debug("[ sh4: pdtrb: read: TODO ]\n");
1495  odata = d->pdtrb;
1496  }
1497  break;
1498 
1499  case SH4_GPIOIC:
1500  if (writeflag == MEM_WRITE)
1501  d->bsc_gpioic = idata;
1502  else
1503  odata = d->bsc_gpioic;
1504  break;
1505 
1506 
1507  /****************************/
1508  /* SCI: Serial Interface */
1509 
1510  case SHREG_SCSPTR:
1511  odata = sh4_sci_access(d, cpu,
1512  writeflag == MEM_WRITE? 1 : 0, idata);
1513 
1514  /*
1515  * TODO
1516  *
1517  * Find out the REAL way to make OpenBSD/landisk 4.1 run
1518  * in a stable manner! This is a SUPER-UGLY HACK which
1519  * just side-steps the real bug.
1520  *
1521  * NOTE: Snapshots of OpenBSD/landisk _after_ 4.1 seem
1522  * to work WITHOUT this hack, but NOT with it!
1523  */
1525 
1526  break;
1527 
1528 
1529  /*********************************/
1530  /* INTC: Interrupt Controller */
1531 
1532  case SH4_ICR:
1533  if (writeflag == MEM_WRITE) {
1534  if (idata & 0x80) {
1535  fatal("SH4 INTC: IRLM not yet "
1536  "supported. TODO\n");
1537  exit(1);
1538  }
1539  }
1540  break;
1541 
1542  case SH4_IPRA:
1543  if (writeflag == MEM_READ)
1544  odata = cpu->cd.sh.intc_ipra;
1545  else {
1546  cpu->cd.sh.intc_ipra = idata;
1548  }
1549  break;
1550 
1551  case SH4_IPRB:
1552  if (writeflag == MEM_READ)
1553  odata = cpu->cd.sh.intc_iprb;
1554  else {
1555  cpu->cd.sh.intc_iprb = idata;
1557  }
1558  break;
1559 
1560  case SH4_IPRC:
1561  if (writeflag == MEM_READ)
1562  odata = cpu->cd.sh.intc_iprc;
1563  else {
1564  cpu->cd.sh.intc_iprc = idata;
1566  }
1567  break;
1568 
1569  case SH4_IPRD:
1570  if (writeflag == MEM_READ)
1571  odata = cpu->cd.sh.intc_iprd;
1572  else {
1573  cpu->cd.sh.intc_iprd = idata;
1575  }
1576  break;
1577 
1578  case SH4_INTPRI00:
1579  if (writeflag == MEM_READ)
1580  odata = cpu->cd.sh.intc_intpri00;
1581  else {
1582  cpu->cd.sh.intc_intpri00 = idata;
1584  }
1585  break;
1586 
1587  case SH4_INTPRI00 + 4:
1588  if (writeflag == MEM_READ)
1589  odata = cpu->cd.sh.intc_intpri04;
1590  else {
1591  cpu->cd.sh.intc_intpri04 = idata;
1593  }
1594  break;
1595 
1596  case SH4_INTPRI00 + 8:
1597  if (writeflag == MEM_READ)
1598  odata = cpu->cd.sh.intc_intpri08;
1599  else {
1600  cpu->cd.sh.intc_intpri08 = idata;
1602  }
1603  break;
1604 
1605  case SH4_INTPRI00 + 0xc:
1606  if (writeflag == MEM_READ)
1607  odata = cpu->cd.sh.intc_intpri0c;
1608  else {
1609  cpu->cd.sh.intc_intpri0c = idata;
1611  }
1612  break;
1613 
1614  case SH4_INTMSK00:
1615  /* Note: Writes can only set bits, not clear them. */
1616  if (writeflag == MEM_READ)
1617  odata = cpu->cd.sh.intc_intmsk00;
1618  else
1619  cpu->cd.sh.intc_intmsk00 |= idata;
1620  break;
1621 
1622  case SH4_INTMSK00 + 4:
1623  /* Note: Writes can only set bits, not clear them. */
1624  if (writeflag == MEM_READ)
1625  odata = cpu->cd.sh.intc_intmsk04;
1626  else
1627  cpu->cd.sh.intc_intmsk04 |= idata;
1628  break;
1629 
1630  case SH4_INTMSKCLR00:
1631  /* Note: Writes can only clear bits, not set them. */
1632  if (writeflag == MEM_WRITE)
1633  cpu->cd.sh.intc_intmsk00 &= ~idata;
1634  break;
1635 
1636  case SH4_INTMSKCLR00 + 4:
1637  /* Note: Writes can only clear bits, not set them. */
1638  if (writeflag == MEM_WRITE)
1639  cpu->cd.sh.intc_intmsk04 &= ~idata;
1640  break;
1641 
1642 
1643  /*************************************************/
1644  /* SCIF: Serial Controller Interface with FIFO */
1645 
1646  case SH4_SCIF_BASE + SCIF_SMR:
1647  if (writeflag == MEM_WRITE) {
1648  d->scif_smr = idata;
1649  } else {
1650  odata = d->scif_smr;
1651  }
1652  break;
1653 
1654  case SH4_SCIF_BASE + SCIF_BRR:
1655  if (writeflag == MEM_WRITE) {
1656  d->scif_brr = idata;
1657  } else {
1658  odata = d->scif_brr;
1659  }
1660  break;
1661 
1662  case SH4_SCIF_BASE + SCIF_SCR:
1663  if (writeflag == MEM_WRITE) {
1664  d->scif_scr = idata;
1665  scif_reassert_interrupts(d);
1666  } else {
1667  odata = d->scif_scr;
1668  }
1669  break;
1670 
1671  case SH4_SCIF_BASE + SCIF_FTDR:
1672  if (writeflag == MEM_WRITE) {
1673  /* Add to TX fifo: */
1674  if (d->scif_tx_fifo_cursize >=
1675  sizeof(d->scif_tx_fifo)) {
1676  fatal("[ SCIF TX fifo overrun! ]\n");
1677  d->scif_tx_fifo_cursize = 0;
1678  }
1679 
1680  d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata;
1682  }
1683  break;
1684 
1685  case SH4_SCIF_BASE + SCIF_SSR:
1686  if (writeflag == MEM_READ) {
1687  odata = d->scif_ssr;
1688  } else {
1689  d->scif_ssr = idata;
1690  scif_reassert_interrupts(d);
1691  }
1692  break;
1693 
1694  case SH4_SCIF_BASE + SCIF_FRDR:
1695  {
1697  if (x == 13)
1698  x = 10;
1699  odata = x < 0? 0 : x;
1701  d->scif_ssr |= SCSSR2_DR;
1702  else
1703  d->scif_ssr &= ~SCSSR2_DR;
1704  scif_reassert_interrupts(d);
1705  }
1706  break;
1707 
1708  case SH4_SCIF_BASE + SCIF_FCR:
1709  if (writeflag == MEM_WRITE) {
1710  d->scif_fcr = idata;
1711  } else {
1712  odata = d->scif_fcr;
1713  }
1714  break;
1715 
1716  case SH4_SCIF_BASE + SCIF_FDR:
1717  /* Nr of bytes in the TX and RX fifos, respectively: */
1718  {
1719  int chars_avail = console_charavail(d->scif_console_handle);
1720  if (chars_avail > 255) {
1721  fatal("[ SH4: Too many chars avail; dropping some ]\n");
1722  chars_avail = 255;
1723  }
1724 
1725  odata = chars_avail | (d->scif_tx_fifo_cursize << 8);
1726  }
1727  break;
1728 
1729  case SH4_SCIF_BASE + SCIF_SPTR:
1730  /* TODO: Implement all bits. */
1731  odata = 0;
1732  break;
1733 
1734  case SH4_SCIF_BASE + SCIF_LSR:
1735  /* TODO: Implement all bits. */
1736  odata = 0;
1737  break;
1738 
1739 
1740  /*************************************************/
1741 
1742  case SH4_CPG_FRQCR: // 0xffc00000 16-bit
1743  if (writeflag == MEM_WRITE)
1744  d->cpg_frqcr = idata;
1745  else
1746  odata = d->cpg_frqcr;
1747  break;
1748 
1749  case SH4_CPG_STBCR: // 0xffc00004 8-bit
1750  if (writeflag == MEM_WRITE)
1751  d->cpg_stbcr = idata;
1752  else
1753  odata = d->cpg_stbcr;
1754  break;
1755 
1756  case SH4_CPG_WTCNT: // 0xffc00008 8/16-bit
1757  if (writeflag == MEM_WRITE)
1758  d->cpg_wtcnt = idata;
1759  else
1760  odata = d->cpg_wtcnt;
1761  break;
1762 
1763  case SH4_CPG_WTCSR: // 0xffc0000c 8/16-bit
1764  if (writeflag == MEM_WRITE)
1765  d->cpg_wtcsr = idata;
1766  else
1767  odata = d->cpg_wtcsr;
1768  break;
1769 
1770  case SH4_CPG_STBCR2: // 0xffc00010 8-bit
1771  if (writeflag == MEM_WRITE)
1772  d->cpg_stbcr2 = idata;
1773  else
1774  odata = d->cpg_stbcr2;
1775  break;
1776 
1777 
1778  /*************************************************/
1779 
1780  case SH4_RSECCNT:
1781  case SH4_RMINCNT:
1782  case SH4_RHRCNT:
1783  case SH4_RWKCNT:
1784  case SH4_RDAYCNT:
1785  case SH4_RMONCNT:
1786  case SH4_RYRCNT:
1787  case SH4_RSECAR:
1788  case SH4_RMINAR:
1789  case SH4_RHRAR:
1790  case SH4_RWKAR:
1791  case SH4_RDAYAR:
1792  case SH4_RMONAR:
1793  if (writeflag == MEM_WRITE) {
1794  d->rtc_reg[(relative_addr - 0xffc80000) / 4] = idata;
1795  } else {
1796  /* TODO: Update rtc_reg based on host's date/time. */
1797  odata = d->rtc_reg[(relative_addr - 0xffc80000) / 4];
1798  }
1799  break;
1800 
1801  case SH4_RCR1:
1802  if (writeflag == MEM_READ)
1803  odata = d->rtc_rcr1;
1804  else {
1805  d->rtc_rcr1 = idata;
1806  if (idata & 0x18) {
1807  fatal("SH4: TODO: RTC interrupt enable\n");
1808  exit(1);
1809  }
1810  }
1811  break;
1812 
1813  case SH4_RCR2:
1814  if (writeflag == MEM_READ)
1815  odata = d->rtc_rcr2;
1816  else {
1817  d->rtc_rcr2 = idata;
1818  // bit 1 (i.e. idata == 0x02) means reset.
1819  if (idata != 0x02) {
1820  debug("[ SH4: TODO: RTC RCR2 value 0x%02x ignored. ]\n", (int)idata);
1821  }
1822  }
1823  break;
1824 
1825 
1826  /*************************************************/
1827 
1828  default:if (writeflag == MEM_READ) {
1829  fatal("[ sh4: read from addr 0x%x ]\n",
1830  (int)relative_addr);
1831  } else {
1832  fatal("[ sh4: write to addr 0x%x: 0x%x ]\n",
1833  (int)relative_addr, (int)idata);
1834  }
1835 
1836 #ifdef SH4_DEBUG
1837  exit(1);
1838 #endif
1839  }
1840 
1841  if (writeflag == MEM_READ)
1842  memory_writemax64(cpu, data, len, odata);
1843 
1844  return 1;
1845 }
1846 
1847 
1849 {
1850  char tmp[200], n[200];
1851  int i;
1852  struct machine *machine = devinit->machine;
1853  struct sh4_data *d;
1854 
1855  CHECK_ALLOCATION(d = (struct sh4_data *) malloc(sizeof(struct sh4_data)));
1856  memset(d, 0, sizeof(struct sh4_data));
1857 
1858 
1859  /*
1860  * Main SH4 device, and misc memory stuff:
1861  */
1862 
1864  SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL);
1865 
1866  /* On-chip RAM/cache: */
1867  dev_ram_init(machine, 0x1e000000, 0x8000, DEV_RAM_RAM, 0x0);
1868 
1869  /* 0xe0000000: Store queues: */
1871  0xe0000000, 0x04000000, dev_sh4_sq_access, d, DM_DEFAULT, NULL);
1872 
1873 
1874  /*
1875  * SCIF (Serial console):
1876  */
1877 
1879  "SH4 SCIF", 1);
1880 
1881  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1883  INTERRUPT_CONNECT(tmp, d->scif_rx_irq);
1884  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1886  INTERRUPT_CONNECT(tmp, d->scif_tx_irq);
1887 
1888 
1889  /*
1890  * Caches (fake):
1891  *
1892  * 0xf0000000 SH4_CCIA I-Cache address array
1893  * 0xf1000000 SH4_CCID I-Cache data array
1894  * 0xf4000000 SH4_CCDA D-Cache address array
1895  * 0xf5000000 SH4_CCDD D-Cache data array
1896  *
1897  * TODO: Implement more correct cache behavior?
1898  */
1899 
1904 
1905  /* 0xf2000000 SH4_ITLB_AA */
1907  0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL);
1908 
1909  /* 0xf3000000 SH4_ITLB_DA1 */
1911  0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL);
1912 
1913  /* 0xf6000000 SH4_UTLB_AA */
1915  0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL);
1916 
1917  /* 0xf7000000 SH4_UTLB_DA1 */
1919  0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL);
1920 
1921 
1922  /*
1923  * PCIC (PCI controller) at 0xfe200000:
1924  */
1925 
1927  N_PCIC_REGS * sizeof(uint32_t), dev_sh4_pcic_access, d,
1928  DM_DEFAULT, NULL);
1929 
1930  /* Initial PCI control register contents: */
1931  d->bsc_bcr2 = BCR2_PORTEN;
1934 
1935  /* Register 16 PCIC interrupts: */
1936  for (i=0; i<N_PCIC_IRQS; i++) {
1937  struct interrupt templ;
1938  snprintf(n, sizeof(n), "%s.pcic.%i",
1939  devinit->interrupt_path, i);
1940  memset(&templ, 0, sizeof(templ));
1941  templ.line = i;
1942  templ.name = n;
1943  templ.extra = d;
1944  templ.interrupt_assert = sh4_pcic_interrupt_assert;
1945  templ.interrupt_deassert = sh4_pcic_interrupt_deassert;
1947 
1948  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1949  devinit->interrupt_path, SH4_INTEVT_IRQ0 + 0x20 * i);
1951  }
1952 
1953  /* Register the PCI bus: */
1954  snprintf(tmp, sizeof(tmp), "%s.pcic", devinit->interrupt_path);
1955  d->pci_data = bus_pci_init(
1956  devinit->machine,
1957  tmp, /* pciirq */
1958  0, /* pci device io offset */
1959  0, /* pci device mem offset */
1960  SH4_PCIC_IO, /* PCI portbase */
1961  SH4_PCIC_MEM, /* PCI membase */
1962  tmp, /* PCI irqbase */
1963  0x00000000, /* ISA portbase */
1964  0x00000000, /* ISA membase */
1965  "TODOisaIrqBase"); /* ISA irqbase */
1966 
1967  /* Return PCI bus pointer, to allow per-machine devices
1968  to be added later: */
1969  devinit->return_ptr = d->pci_data;
1970 
1971 
1972  /*
1973  * Timer:
1974  */
1975 
1976  d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d);
1977  machine_add_tickfunction(devinit->machine, dev_sh4_tick, d,
1978  SH4_TICK_SHIFT);
1979 
1980  /* Initial Timer values, according to the SH7750 manual: */
1981  d->tcor[0] = 0xffffffff; d->tcnt[0] = 0xffffffff;
1982  d->tcor[1] = 0xffffffff; d->tcnt[1] = 0xffffffff;
1983  d->tcor[2] = 0xffffffff; d->tcnt[2] = 0xffffffff;
1984 
1985  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1987  if (!interrupt_handler_lookup(tmp, &d->timer_irq[0])) {
1988  fatal("Could not find interrupt '%s'.\n", tmp);
1989  exit(1);
1990  }
1991  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1993  if (!interrupt_handler_lookup(tmp, &d->timer_irq[1])) {
1994  fatal("Could not find interrupt '%s'.\n", tmp);
1995  exit(1);
1996  }
1997  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1999  if (!interrupt_handler_lookup(tmp, &d->timer_irq[2])) {
2000  fatal("Could not find interrupt '%s'.\n", tmp);
2001  exit(1);
2002  }
2003 
2004 
2005  // The RTC RCR2 register is "basically" initialized to 0x09, with
2006  // some bit undefined. :-) According to the manual.
2007  d->rtc_rcr2 = 0x09;
2008 
2009 
2010  /*
2011  * Bus State Controller initial values, according to the
2012  * SH7760 manual:
2013  */
2014 
2015  d->bsc_bcr2 = 0x3ffc;
2016  d->bsc_wcr1 = 0x77777777;
2017  d->bsc_wcr2 = 0xfffeefff;
2018  d->bsc_wcr3 = 0x77777777;
2019 
2020  return 1;
2021 }
2022 
SH4_UTLB_AA_VPN_MASK
#define SH4_UTLB_AA_VPN_MASK
Definition: sh4_mmu.h:128
SCSPTR_SPB1IO
#define SCSPTR_SPB1IO
Definition: sh4_scireg.h:83
TCR_ICPE1
#define TCR_ICPE1
Definition: sh4_tmureg.h:77
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Definition: sh4_mmu.h:94
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Definition: bus_pci.cc:95
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Definition: dev_sh4.cc:172
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Definition: sh4_scifreg.h:77
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Definition: dev_sh4.cc:161
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Definition: dev_sh4.cc:544
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Definition: sh4_pcicreg.h:51
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Definition: dev_sh4.cc:116
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Definition: sh4_mmu.h:129
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Definition: sh4_scifreg.h:72
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Definition: sh4_scifreg.h:135
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Definition: sh4_mmu.h:67
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Definition: dev_sh4.cc:143
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Definition: dev_sh4.cc:90
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Definition: devices.h:364
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Definition: sh4_scifreg.h:73
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Definition: sh4_scifreg.h:70
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Definition: sh4_tmureg.h:79
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Definition: dev_sh4.cc:129
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Definition: sh4_pcicreg.h:95
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Definition: sh4_bscreg.h:79
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Definition: dev_sh4.cc:144
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Definition: sh4_pcicreg.h:103
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Definition: sh4_dmacreg.h:120
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Definition: cpu_sh.h:166
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Definition: sh4_dmacreg.h:47
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Definition: dev_sh4.cc:118
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struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:355
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Definition: sh4_scireg.h:84
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Definition: sh4_dmacreg.h:128
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Definition: dev_sh4.cc:125
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Definition: sh4_cache.h:67
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Definition: sh4_dmacreg.h:70
PCIC_REG
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Definition: dev_sh4.cc:74
SH4_CPG_STBCR2
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Definition: dev_sh4.cc:92
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Definition: sh4_mmu.h:47
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Definition: debugger_cmds.cc:1189
PCI_CLASS_CODE
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Definition: pcireg.h:146
MEM_WRITE
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Definition: memory.h:117
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Definition: sh4_rtcreg.h:68
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Definition: sh4_pcicreg.h:50
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Definition: sh4_bscreg.h:63
N_SH4_TIMERS
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Definition: dev_sh4.cc:69
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Definition: cpu_sh.h:165
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Definition: sh4_scifreg.h:140
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Definition: sh4_dmacreg.h:79
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Definition: sh4_mmu.h:56
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Definition: sh4_tmureg.h:55
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Definition: sh4_rtcreg.h:59
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uint8_t scif_tx_fifo[SCIF_TX_FIFO_SIZE+1]
Definition: dev_sh4.cc:108
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Definition: sh4_dmacreg.h:74
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Definition: machine.cc:280
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Definition: sh4_dmacreg.h:122
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Definition: sh4_pcicreg.h:105
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Definition: sh4_bscreg.h:65
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Definition: sh4_pcicreg.h:102
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Definition: sh4_tmureg.h:57
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Definition: sh4_tmureg.h:52
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Definition: sh4_scifreg.h:68
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Definition: cpu.h:483
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Definition: dev_sh4.cc:89
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Definition: dev_sh4.cc:106
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Definition: sh4_tmureg.h:51
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Definition: pcireg.h:213
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Definition: sh4_rtcreg.h:60
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Definition: sh4_exception.h:142
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Definition: device.h:50
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Definition: dev_sh4.cc:163
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Definition: sh4_mmu.h:50
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Definition: sh4_bscreg.h:80
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Definition: sh4_mmu.h:125
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Definition: sh4_dmacreg.h:42
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PHYSICAL
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Definition: memory.h:126
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Definition: dev_sh4.cc:274
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Definition: main.cc:152
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Definition: sh4_mmu.h:103
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Definition: dev_sh4.cc:166
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Definition: sh4_pcicreg.h:107
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Definition: dev_sh4.cc:111
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Definition: sh4_dmacreg.h:123
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Definition: sh4_dmacreg.h:119
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Definition: sh4_dmacreg.h:130
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Definition: sh4_scifreg.h:74
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Definition: dev_sh4.cc:170
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Definition: sh4_dmacreg.h:77
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Definition: sh4_dmacreg.h:52
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Definition: cpu_sh.h:150
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Definition: dev_sh4.cc:145
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Definition: sh4_dmacreg.h:129
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Definition: sh4_exception.h:90
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Definition: sh4_bscreg.h:77
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