dreamcast_pvr.h Source File
Back to the index.
Go to the documentation of this file.
4 #ifndef DREAMCAST_PVR_H
5 #define DREAMCAST_PVR_H
77 #define PVRREG_FBSTART 0x05000000
78 #define PVRREG_REGSTART 0x005f8000
80 #define PVRREG_REGSIZE 0x00002000
83 #define PVRREG_ID 0x00
85 #define PVRREG_REVISION 0x04
86 #define PVR_REVISION_MINOR_MASK 0xf
87 #define PVR_REVISION_MAJOR_MASK 0xf0
88 #define PVR_REVISION_MAJOR_SHIFT 4
90 #define PVRREG_RESET 0x08
91 #define PVR_RESET_TA 0x00000001
92 #define PVR_RESET_PVR 0x00000002
93 #define PVR_RESET_BUS 0x00000004
95 #define PVRREG_STARTRENDER 0x14
97 #define PVRREG_OB_ADDR 0x20
102 #define PVR_OB_ADDR_MASK 0x00f80000
104 #define PVRREG_TILEBUF_ADDR 0x2c
105 #define PVR_TILEBUF_ADDR_MASK 0x00fffff8
107 #define PVRREG_SPANSORT 0x30
108 #define PVR_SPANSORT_SPAN0 0x00000001
109 #define PVR_SPANSORT_SPAN1 0x00000100
110 #define PVR_SPANSORT_TSP_CACHE_ENABLE 0x00010000
112 #define PVRREG_BRDCOLR 0x40
113 #define BRDCOLR_BLUE(x) ((x) << 0)
114 #define BRDCOLR_GREEN(x) ((x) << 8)
115 #define BRDCOLR_RED(x) ((x) << 16)
117 #define PVRREG_DIWMODE 0x44
118 #define DIWMODE_DE (1U << 0)
119 #define DIWMODE_SD (1U << 1)
120 #define DIWMODE_COL(x) ((x) << 2)
121 #define DIWMODE_COL_RGB555 DIWMODE_COL(0)
122 #define DIWMODE_COL_RGB565 DIWMODE_COL(1)
123 #define DIWMODE_COL_RGB888 DIWMODE_COL(2)
124 #define DIWMODE_COL_ARGB888 DIWMODE_COL(3)
125 #define DIWMODE_C (1U << 23)
126 #define DIWMODE_DE_MASK 0x00000001
127 #define DIWMODE_SD_MASK 0x00000002
128 #define DIWMODE_COL_MASK 0x0000000c
129 #define DIWMODE_COL_SHIFT 2
130 #define DIWMODE_EX_MASK 0x00000070
131 #define DIWMODE_EX_SHIFT 4
132 #define DIWMODE_TH_MASK 0x0000ff00
133 #define DIWMODE_TH_SHIFT 8
134 #define DIWMODE_SL_MASK 0x003f0000
135 #define DIWMODE_SL_SHIFT 16
136 #define DIWMODE_SE_MASK 0x00400000
137 #define DIWMODE_C_MASK 0x00800000
139 #define PVRREG_FB_RENDER_CFG 0x48
140 #define FB_RENDER_CFG_RENDER_MODE_MASK 0x07
150 #define FB_RENDER_CFG_DITHER (1 << 3)
151 #define FB_RENDER_CFG_ALPHA_MASK 0x0000ff00
152 #define FB_RENDER_CFG_ALPHA_SHFIT 8
153 #define FB_RENDER_CFG_THRESHOLD_MASK 0x00ff0000
154 #define FB_RENDER_CFG_THRESHOLD_SHFIT 8
156 #define PVRREG_FB_RENDER_MODULO 0x4c
157 #define FB_RENDER_MODULO_MASK 0x000001ff
160 #define PVRREG_DIWADDRL 0x50
162 #define PVRREG_DIWADDRS 0x54
164 #define PVRREG_DIWSIZE 0x5c
165 #define DIWSIZE_DPL(x) ((x) << 0)
166 #define DIWSIZE_LPF(x) ((x) << 10)
167 #define DIWSIZE_MODULO(x) ((x) << 20)
168 #define DIWSIZE_MASK 0x3ff
169 #define DIWSIZE_DPL_SHIFT 0
170 #define DIWSIZE_LPF_SHIFT 10
171 #define DIWSIZE_MODULO_SHIFT 20
173 #define PVRREG_FB_RENDER_ADDR1 0x60
175 #define PVRREG_FB_RENDER_ADDR2 0x64
177 #define PVRREG_FB_CLIP_X 0x68
178 #define PVRREG_FB_CLIP_Y 0x6c
179 #define FB_CLIP_XY_MIN_MASK 0x000007ff
180 #define FB_CLIP_XY_MAX_MASK 0x07ff0000
181 #define FB_CLIP_XY_MAX_SHIFT 16
183 #define PVRREG_SHADOW 0x74
184 #define SHADOW_INTENSITY_MASK 0x000000ff
185 #define SHADOW_ENABLE (1 << 8)
187 #define PVRREG_OBJECT_CLIP 0x78
189 #define PVRREG_OB_CFG 0x7c
191 #define PVRREG_UNKNOWN_80 0x80
192 #define PVRREG_UNKNOWN_84 0x84
194 #define PVRREG_BGPLANE_Z 0x88
196 #define PVRREG_BGPLANE_CFG 0x8c
198 #define PVRREG_ISP_CFG 0x98
200 #define PVRREG_VRAM_CFG1 0xa0
201 #define VRAM_CFG1_GOOD_REFRESH_VALUE 0x20
203 #define PVRREG_VRAM_CFG2 0xa4
204 #define VRAM_CFG2_UNKNOWN_MAGIC 0x0000001f
206 #define PVRREG_VRAM_CFG3 0xa8
207 #define VRAM_CFG3_UNKNOWN_MAGIC 0x15d1c951
209 #define PVRREG_FOG_TABLE_COL 0xb0
210 #define PVRREG_FOG_VERTEX_COL 0xb4
211 #define PVRREG_FOG_DENSITY 0xb8
213 #define PVRREG_CLAMP_MAX 0xbc
214 #define PVRREG_CLAMP_MIN 0xc0
216 #define PVRREG_HPOS_IRQ 0xc8
218 #define PVRREG_RASEVTPOS 0xcc
219 #define RASEVTPOS_POS2_MASK 0x000003ff
220 #define RASEVTPOS_POS1_MASK 0x03ff0000
221 #define RASEVTPOS_POS1_SHIFT 16
222 #define RASEVTPOS_BOTTOM(x) ((x) << 0)
223 #define RASEVTPOS_TOP(x) ((x) << 16)
225 #define PVRREG_SYNCCONF 0xd0
226 #define SYNCCONF_VP (1U << 0)
227 #define SYNCCONF_HP (1U << 1)
228 #define SYNCCONF_I (1U << 4)
229 #define SYNCCONF_BC(x) (1U << 6)
230 #define SYNCCONF_VO (1U << 8)
231 #define SYNCCONF_VO_MASK 0x00000100
232 #define SYNCCONF_BC_MASK 0x000000c0
233 #define SYNCCONF_BC_SHIFT 6
234 #define SYNCCONF_BC_VGA 0
235 #define SYNCCONF_BC_NTSC 1
236 #define SYNCCONF_BC_PAL 2
237 #define SYNCCONF_I_MASK 0x00000010
238 #define SYNCCONF_HP_MASK 0x00000004
239 #define SYNCCONF_VP_MASK 0x00000002
241 #define PVRREG_BRDHORZ 0xd4
242 #define BRDHORZ_STOP_MASK 0x0000ffff
243 #define BRDHORZ_START_MASK 0xffff0000
244 #define BRDHORZ_START_SHIFT 16
245 #define BRDHORZ_STOP(x) ((x) << 0)
246 #define BRDHORZ_START(x) ((x) << 16)
248 #define PVRREG_SYNCSIZE 0xd8
249 #define SYNCSIZE_H_MASK 0x0000ffff
250 #define SYNCSIZE_V_MASK 0xffff0000
251 #define SYNCSIZE_V_SHIFT 16
252 #define SYNCSIZE_H(x) ((x) << 0)
253 #define SYNCSIZE_V(x) ((x) << 16)
255 #define PVRREG_BRDVERT 0xdc
256 #define BRDVERT_STOP_MASK 0x0000ffff
257 #define BRDVERT_START_MASK 0xffff0000
258 #define BRDVERT_START_SHIFT 16
259 #define BRDVERT_STOP(x) ((x) << 0)
260 #define BRDVERT_START(x) ((x) << 16)
262 #define PVRREG_SYNCH_WIDTH 0xe0
264 #define PVRREG_TSP_CFG 0xe4
265 #define TSP_CFG_CBE (1 << 17)
266 #define TSP_CFG_IE (1 << 16)
267 #define TSP_CFG_MODULO_MASK 0x1f
269 #define PVRREG_DIWCONF 0xe8
270 #define DIWCONF_BLANK (1U << 3)
271 #define DIWCONF_LR (1U << 8)
272 #define DIWCONF_MAGIC_MASK 0x003f0000
273 #define DIWCONF_MAGIC (22 << 16)
275 #define PVRREG_DIWHSTRT 0xec
276 #define DIWVSTRT_HPOS_MASK 0x000003ff
278 #define PVRREG_DIWVSTRT 0xf0
279 #define DIWVSTRT_V1_MASK 0x000003ff
280 #define DIWVSTRT_V2_MASK 0x03ff0000
281 #define DIWVSTRT_V2_SHIFT 16
282 #define DIWVSTRT_V1(x) ((x) << 0)
283 #define DIWVSTRT_V2(x) ((x) << 16)
285 #define PVRREG_SCALER_CFG 0xf4
287 #define PVRREG_PALETTE_CFG 0x108
288 #define PVR_PALETTE_CFG_MODE_MASK 0x3
289 #define PVR_PALETTE_CFG_MODE_ARGB1555 0x0
290 #define PVR_PALETTE_CFG_MODE_RGB565 0x1
291 #define PVR_PALETTE_CFG_MODE_ARGB4444 0x2
292 #define PVR_PALETTE_CFG_MODE_ARGB8888 0x3
294 #define PVRREG_SYNC_STAT 0x10c
295 #define PVR_SYNC_STAT_VPOS_MASK 0x000003ff
296 #define PVR_SYNC_STAT_INTERLACE_FIELD_EVEN 0x00000400
297 #define PVR_SYNC_STAT_HBLANK 0x00001000
298 #define PVR_SYNC_STAT_VBLANK 0x00002000
300 #define PVRREG_MAGIC_110 0x110
301 #define MAGIC_110_VALUE 0x93f39
303 #define PVRREG_TA_LUMINANCE 0x118
305 #define PVRREG_TA_OPB_START 0x124
306 #define TA_OPB_START_MASK 0x00ffff80
308 #define PVRREG_TA_OB_START 0x128
309 #define TA_OB_START_MASK 0x00fffff8
311 #define PVRREG_TA_OPB_END 0x12c
312 #define TA_OPB_END_MASK 0x00ffff80
314 #define PVRREG_TA_OB_END 0x130
315 #define TA_OB_END_MASK 0x00fffff8
317 #define PVRREG_TA_OPB_POS 0x134
318 #define TA_OPB_POS_MASK 0x00ffff80
320 #define PVRREG_TA_OB_POS 0x138
321 #define TA_OB_POS_MASK 0x00fffff8
323 #define PVRREG_TILEBUF_SIZE 0x13c
324 #define TILEBUF_SIZE_HEIGHT_MASK 0xffff0000
325 #define TILEBUF_SIZE_HEIGHT_SHIFT 16
326 #define TILEBUF_SIZE_WIDTH_MASK 0x0000ffff
328 #define PVRREG_TA_OPB_CFG 0x140
329 #define TA_OPB_CFG_OPAQUEPOLY_MASK 0x00000003
330 #define TA_OPB_CFG_OPAQUEMOD_MASK 0x00000030
331 #define TA_OPB_CFG_OPAQUEMOD_SHIFT 4
332 #define TA_OPB_CFG_TRANSPOLY_MASK 0x00000300
333 #define TA_OPB_CFG_TRANSPOLY_SHIFT 8
334 #define TA_OPB_CFG_TRANSMOD_MASK 0x00003000
335 #define TA_OPB_CFG_TRANSMOD_SHIFT 12
336 #define TA_OPB_CFG_PUNCHTHROUGH_MASK 0x00030000
337 #define TA_OPB_CFG_PUNCHTHROUGH_SHIFT 16
338 #define TA_OPB_CFG_OPBDIR 0x00100000
340 #define PVRREG_TA_INIT 0x144
341 #define PVR_TA_INIT 0x80000000
343 #define PVRREG_YUV_ADDR 0x148
344 #define PVR_YUV_ADDR_MASK 0x00ffffe0
346 #define PVRREG_YUV_CFG1 0x14c
349 #define PVRREG_YUV_STAT 0x150
351 #define PVR_YUV_STAT_BLOCKS_MASK 0x1fff
353 #define PVRREG_TA_OPL_REINIT 0x160
354 #define PVR_TA_OPL_REINIT 0x80000000
356 #define PVRREG_TA_OPL_INIT 0x164
358 #define PVR_TA_OPL_INIT_MASK 0x00ffff80
360 #define PVRREG_FOG_TABLE 0x0200
361 #define PVR_FOG_TABLE_SIZE 0x0200
363 #define PVRREG_PALETTE 0x1000
364 #define PVR_PALETTE_SIZE 0x1000
Generated on Tue Aug 25 2020 19:25:06 for GXemul by
1.8.18