dev_dec_ioasic.cc Source File

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dev_dec_ioasic.cc
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1 /*
2  * Copyright (C) 2004-2018 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: IOASIC device used in some DECstation machines
29  *
30  * TODO: Lots of stuff, such as DMA and all bits in the control registers.
31  */
32 
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 
37 #include "cpu.h"
38 #include "devices.h"
39 #include "interrupt.h"
40 #include "memory.h"
41 #include "misc.h"
42 
43 #include "thirdparty/dec_kn03.h"
45 
46 
47 #define IOASIC_DEBUG
48 /* #define debug fatal */
49 
50 
52 {
53  // printf("[ intr = 0x%08x, imsk = 0x%08x ]\n", d->intr, d->imsk);
54 
55  if (d->intr & d->imsk && !d->int_asserted) {
56  d->int_asserted = 1;
57  d->irq->interrupt_assert(d->irq);
58  }
59  if (!(d->intr & d->imsk) && d->int_asserted) {
60  d->int_asserted = 0;
61  d->irq->interrupt_deassert(d->irq);
62  }
63 }
64 
65 
66 DEVICE_ACCESS(dec_ioasic)
67 {
68  struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra;
69  uint64_t idata = 0, odata = 0;
70  // uint64_t curptr;
71  // uint32_t csr;
72  // int dma_len, dma_res, regnr;
73 
74  if (writeflag == MEM_WRITE)
75  idata = memory_readmax64(cpu, data, len);
76 
77  switch (relative_addr) {
78 
79  case 0:
80  /* NetBSD/pmax and OpenBSD/pmax read from this address. */
81  break;
82 
83  case IOASIC_SCSI_DMAPTR:
84  if (writeflag == MEM_WRITE)
85  d->scsi_dmaptr = idata;
86  else
87  odata = d->scsi_dmaptr;
88 
89  debug("[ dec_ioasic: %s SCSI_DMAPTR, data=0x%08x ]\n",
90  writeflag == MEM_WRITE ? "write to" : "read from",
91  writeflag == MEM_WRITE ? idata : odata);
92  break;
93 
95  if (writeflag == MEM_WRITE)
96  d->scsi_nextptr = idata;
97  else
98  odata = d->scsi_nextptr;
99 
100  debug("[ dec_ioasic: %s SCSI_NEXTPTR, data=0x%08x ]\n",
101  writeflag == MEM_WRITE ? "write to" : "read from",
102  writeflag == MEM_WRITE ? idata : odata);
103  break;
104 
105  case IOASIC_LANCE_DMAPTR:
106  if (writeflag == MEM_WRITE)
107  d->lance_dmaptr = idata;
108  else
109  odata = d->lance_dmaptr;
110 
111  debug("[ dec_ioasic: %s LANCE_DMAPTR, data=0x%08x ]\n",
112  writeflag == MEM_WRITE ? "write to" : "read from",
113  writeflag == MEM_WRITE ? idata : odata);
114  break;
115 
117  if (writeflag == MEM_WRITE)
118  d->floppy_dmaptr = idata;
119  else
120  odata = d->floppy_dmaptr;
121 
122  debug("[ dec_ioasic: %s FLOPPY_DMAPTR, data=0x%08x ]\n",
123  writeflag == MEM_WRITE ? "write to" : "read from",
124  writeflag == MEM_WRITE ? idata : odata);
125  break;
126 
128  if (writeflag == MEM_WRITE)
129  d->isdn_x_dmaptr = idata;
130  else
131  odata = d->isdn_x_dmaptr;
132 
133  debug("[ dec_ioasic: %s ISDN_X_DMAPTR, data=0x%08x ]\n",
134  writeflag == MEM_WRITE ? "write to" : "read from",
135  writeflag == MEM_WRITE ? idata : odata);
136  break;
137 
139  if (writeflag == MEM_WRITE)
140  d->isdn_x_nextptr = idata;
141  else
142  odata = d->isdn_x_nextptr;
143 
144  debug("[ dec_ioasic: %s ISDN_X_NEXTPTR, data=0x%08x ]\n",
145  writeflag == MEM_WRITE ? "write to" : "read from",
146  writeflag == MEM_WRITE ? idata : odata);
147  break;
148 
150  if (writeflag == MEM_WRITE)
151  d->isdn_r_dmaptr = idata;
152  else
153  odata = d->isdn_r_dmaptr;
154 
155  debug("[ dec_ioasic: %s ISDN_R_DMAPTR, data=0x%08x ]\n",
156  writeflag == MEM_WRITE ? "write to" : "read from",
157  writeflag == MEM_WRITE ? idata : odata);
158  break;
159 
161  if (writeflag == MEM_WRITE)
162  d->isdn_r_nextptr = idata;
163  else
164  odata = d->isdn_r_nextptr;
165 
166  debug("[ dec_ioasic: %s ISDN_R_NEXTPTR, data=0x%08x ]\n",
167  writeflag == MEM_WRITE ? "write to" : "read from",
168  writeflag == MEM_WRITE ? idata : odata);
169  break;
170 
171  case IOASIC_CSR:
172  if (writeflag == MEM_WRITE)
173  d->csr = idata;
174  else
175  odata = d->csr;
176 
177  debug("[ dec_ioasic: %s CSR, data=0x%08x ]\n",
178  writeflag == MEM_WRITE ? "write to" : "read from",
179  writeflag == MEM_WRITE ? idata : odata);
180 #if 0
181  if (writeflag == MEM_WRITE) {
182  csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10];
183 
184  d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &=
186 
187  if (csr & IOASIC_CSR_DMAEN_T2) {
188  /* Transmit data: */
189  curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR -
190  IOASIC_SLOT_1_START) / 0x10] >> 3)
191  | ((d->reg[(IOASIC_SCC_T2_DMAPTR -
192  IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
193  dma_len = 0x1000 - (curptr & 0xffc);
194 
195  if ((curptr & 0xfff) == 0)
196  break;
197 
198  if (d->dma_func[3] != NULL) {
199  d->dma_func[3](cpu,
200  d->dma_func_extra[3], curptr,
201  dma_len, 1);
202  } else
203  fatal("[ dec_ioasic: DMA tx: data @ "
204  "%08x, len %i bytes, but no "
205  "handler? ]\n", (int)curptr,
206  dma_len);
207 
208  /* and signal the end of page: */
209  d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) /
210  0x10] |= IOASIC_INTR_T2_PAGE_END;
211 
212  d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) /
213  0x10] &= ~IOASIC_CSR_DMAEN_T2;
214  curptr |= 0xfff;
215  curptr ++;
216 
217  d->reg[(IOASIC_SCC_T2_DMAPTR -
218  IOASIC_SLOT_1_START) / 0x10] = ((curptr <<
219  3) & ~0x1f) | ((curptr >> 29) & 0x1f);
220  }
221 
222  if (csr & IOASIC_CSR_DMAEN_R2) {
223  /* Receive data: */
224  curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR -
225  IOASIC_SLOT_1_START) / 0x10] >> 3)
226  | ((d->reg[(IOASIC_SCC_R2_DMAPTR -
227  IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29);
228  dma_len = 0x1000 - (curptr & 0xffc);
229 
230  dma_res = 0;
231  if (d->dma_func[3] != NULL) {
232  dma_res = d->dma_func[3](cpu,
233  d->dma_func_extra[3], curptr,
234  dma_len, 0);
235  } else
236  fatal("[ dec_ioasic: DMA tx: data @ "
237  "%08x, len %i bytes, but no "
238  "handler? ]\n", (int)curptr,
239  dma_len);
240 
241  /* and signal the end of page: */
242  if (dma_res > 0) {
243  if ((curptr & 0x800) != ((curptr +
244  dma_res) & 0x800))
245  d->reg[(IOASIC_INTR -
246  IOASIC_SLOT_1_START) / 0x10]
248  curptr += dma_res;
249 /* d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START
250  ) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */
251  d->reg[(IOASIC_SCC_R2_DMAPTR -
252  IOASIC_SLOT_1_START) / 0x10] =
253  ((curptr << 3) & ~0x1f) | ((curptr
254  >> 29) & 0x1f);
255  }
256  }
257  }
258 #endif
259  break;
260 
261  case IOASIC_INTR:
262  if (writeflag == MEM_WRITE) {
263  /* Clear bits on write? */
264  d->intr &= ~idata;
266  } else {
267  odata = d->intr;
268 
269  /* Note/TODO: How about other models than KN03? */
270  //if (!d->rackmount_flag)
271  // odata |= KN03_INTR_PROD_JUMPER;
272  }
273 
274  debug("[ dec_ioasic: %s INTR, data=0x%08x ]\n",
275  writeflag == MEM_WRITE ? "write to" : "read from",
276  writeflag == MEM_WRITE ? idata : odata);
277 
278  break;
279 
280  case IOASIC_IMSK:
281  if (writeflag == MEM_WRITE) {
282  d->imsk = idata;
284  } else {
285  odata = d->imsk;
286  }
287 
288  debug("[ dec_ioasic: %s IMSK, data=0x%08x ]\n",
289  writeflag == MEM_WRITE ? "write to" : "read from",
290  writeflag == MEM_WRITE ? idata : odata);
291  break;
292 
293  case IOASIC_ISDN_X_DATA:
294  if (writeflag == MEM_WRITE)
295  d->isdn_x_data = idata;
296  else
297  odata = d->isdn_x_data;
298 
299  debug("[ dec_ioasic: %s ISDN_X_DATA, data=0x%08x ]\n",
300  writeflag == MEM_WRITE ? "write to" : "read from",
301  writeflag == MEM_WRITE ? idata : odata);
302  break;
303 
304  case IOASIC_ISDN_R_DATA:
305  if (writeflag == MEM_WRITE)
306  d->isdn_r_data = idata;
307  else
308  odata = d->isdn_r_data;
309 
310  debug("[ dec_ioasic: %s ISDN_R_DATA, data=0x%08x ]\n",
311  writeflag == MEM_WRITE ? "write to" : "read from",
312  writeflag == MEM_WRITE ? idata : odata);
313  break;
314 
315  case IOASIC_LANCE_DECODE:
316  if (writeflag == MEM_WRITE)
317  d->lance_decode = idata;
318  else
319  odata = d->lance_decode;
320 
321  debug("[ dec_ioasic: %s LANCE_DECODE, data=0x%08x ]\n",
322  writeflag == MEM_WRITE ? "write to" : "read from",
323  writeflag == MEM_WRITE ? idata : odata);
324  break;
325 
326  case IOASIC_SCSI_DECODE:
327  if (writeflag == MEM_WRITE)
328  d->scsi_decode = idata;
329  else
330  odata = d->scsi_decode;
331 
332  debug("[ dec_ioasic: %s SCSI_DECODE, data=0x%08x ]\n",
333  writeflag == MEM_WRITE ? "write to" : "read from",
334  writeflag == MEM_WRITE ? idata : odata);
335  break;
336 
337  case IOASIC_SCC0_DECODE:
338  if (writeflag == MEM_WRITE)
339  d->scc0_decode = idata;
340  else
341  odata = d->scc0_decode;
342 
343  debug("[ dec_ioasic: %s SCC0_DECODE, data=0x%08x ]\n",
344  writeflag == MEM_WRITE ? "write to" : "read from",
345  writeflag == MEM_WRITE ? idata : odata);
346  break;
347 
348  case IOASIC_SCC1_DECODE:
349  if (writeflag == MEM_WRITE)
350  d->scc1_decode = idata;
351  else
352  odata = d->scc1_decode;
353 
354  debug("[ dec_ioasic: %s SCC1_DECODE, data=0x%08x ]\n",
355  writeflag == MEM_WRITE ? "write to" : "read from",
356  writeflag == MEM_WRITE ? idata : odata);
357  break;
358 
360  if (writeflag == MEM_WRITE)
361  d->floppy_decode = idata;
362  else
363  odata = d->floppy_decode;
364 
365  debug("[ dec_ioasic: %s FLOPPY_DECODE, data=0x%08x ]\n",
366  writeflag == MEM_WRITE ? "write to" : "read from",
367  writeflag == MEM_WRITE ? idata : odata);
368  break;
369 
370  case IOASIC_SCSI_SCR:
371  if (writeflag == MEM_WRITE)
372  d->scsi_scr = idata;
373  else
374  odata = d->scsi_scr;
375 
376  debug("[ dec_ioasic: %s SCSI_SCR, data=0x%08x ]\n",
377  writeflag == MEM_WRITE ? "write to" : "read from",
378  writeflag == MEM_WRITE ? idata : odata);
379  break;
380 
381  case IOASIC_SCSI_SDR0:
382  if (writeflag == MEM_WRITE)
383  d->scsi_sdr0 = idata;
384  else
385  odata = d->scsi_sdr0;
386 
387  debug("[ dec_ioasic: %s SCSI_SDR0, data=0x%08x ]\n",
388  writeflag == MEM_WRITE ? "write to" : "read from",
389  writeflag == MEM_WRITE ? idata : odata);
390  break;
391 
392  case IOASIC_SCSI_SDR1:
393  if (writeflag == MEM_WRITE)
394  d->scsi_sdr1 = idata;
395  else
396  odata = d->scsi_sdr1;
397 
398  debug("[ dec_ioasic: %s SCSI_SDR1, data=0x%08x ]\n",
399  writeflag == MEM_WRITE ? "write to" : "read from",
400  writeflag == MEM_WRITE ? idata : odata);
401  break;
402 
403 
404  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x00:
405  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x04:
406  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x08:
407  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x0c:
408  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x10:
409  case IOASIC_SYS_ETHER_ADDRESS(0) + 0x14:
410  /* Station's ethernet address: */
411  if (writeflag == MEM_WRITE) {
412  fatal("[ dec_ioasic: attempt to write to the station's"
413  " ethernet address. ignored for now. ]\n");
414  } else {
415  odata = ((relative_addr - IOASIC_SYS_ETHER_ADDRESS(0)) / 4 + 1) * 0x10;
416  }
417  break;
418 
419  /* The DECstation 5000/125's PROM uses these for cache testing. TODO. */
420  case 0x0f004:
421  case 0x1f008:
422  case 0x2f00c:
423  case 0x3f010:
424  case 0x4f014:
425  case 0x5f018:
426  case 0x6f01c:
427  case 0x7f020:
428  case 0x8f024:
429  case 0x9f028:
430  case 0xaf02c:
431  case 0xbf030:
432  break;
433 
434  default:
435  if (writeflag == MEM_WRITE)
436  fatal("[ dec_ioasic: unimplemented write to address "
437  "0x%llx, data=0x%08llx ]\n",
438  (long long)relative_addr, (long long)idata);
439  else
440  fatal("[ dec_ioasic: unimplemented read from address "
441  "0x%llx ]\n", (long long)relative_addr);
442  // exit(1);
443  }
444 
445  if (writeflag == MEM_READ)
446  memory_writemax64(cpu, data, len, odata);
447 
448  return 1;
449 }
450 
451 
452 /*
453  * dev_dec_ioasic_init():
454  *
455  * For DECstation "type 4", the rackmount_flag selects which model type
456  * the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag
457  * is non-zero). It is probably not meaningful on other machines than
458  * type 4.
459  */
461  struct memory *mem, uint64_t baseaddr, int rackmount_flag, struct interrupt* irqp)
462 {
463  struct dec_ioasic_data *d;
464 
465  CHECK_ALLOCATION(d = (struct dec_ioasic_data *) malloc(sizeof(struct dec_ioasic_data)));
466  memset(d, 0, sizeof(struct dec_ioasic_data));
467 
469  d->irq = irqp;
470 
471  memory_device_register(mem, "dec_ioasic", baseaddr,
473  DM_DEFAULT, NULL);
474 
475  return d;
476 }
477 
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#define IOASIC_SCSI_DMAPTR
Definition: tc_ioasicreg.h:96
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