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Macros | |
#define | MEC_MAC_CONTROL 0x00 |
#define | MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */ |
#define | MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */ |
#define | MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */ |
#define | MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */ |
#define | MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */ |
#define | MEC_MAC_FILTER_MASK 0x0000000000000060 |
#define | MEC_MAC_FILTER_STATION 0x0000000000000000 |
#define | MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020 |
#define | MEC_MAC_FILTER_ALLMULTI 0x0000000000000040 |
#define | MEC_MAC_FILTER_PROMISC 0x0000000000000060 |
#define | MEC_MAC_LINK_FAILURE 0x0000000000000080 |
#define | MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */ |
#define | MEC_MAC_IPGT_SHIFT 8 |
#define | MEC_MAC_IPGR1 0x00000000003f8000 |
#define | MEC_MAC_IPGR1_SHIFT 15 |
#define | MEC_MAC_IPGR2 0x000000001fc00000 |
#define | MEC_MAC_IPGR2_SHIFT 22 |
#define | MEC_MAC_REVISION 0x00000000e0000000 |
#define | MEC_MAC_REVISION_SHIFT 29 |
#define | MEC_MAC_IPG_DEFAULT |
#define | MEC_INT_STATUS 0x08 |
#define | MEC_INT_STATUS_MASK 0x00000000000000ff |
#define | MEC_INT_TX_EMPTY 0x0000000000000001 |
#define | MEC_INT_TX_PACKET_SENT 0x0000000000000002 |
#define | MEC_INT_TX_LINK_FAIL 0x0000000000000004 |
#define | MEC_INT_TX_MEM_ERROR 0x0000000000000008 |
#define | MEC_INT_TX_ABORT 0x0000000000000010 |
#define | MEC_INT_RX_THRESHOLD 0x0000000000000020 |
#define | MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040 |
#define | MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080 |
#define | MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00 |
#define | MEC_INT_RX_MCL_FIFO_SHIFT 8 |
#define | MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000 |
#define | MEC_INT_TX_RING_BUFFER_SHIFT 16 |
#define | MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000 |
#define | MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000 |
#define | MEC_DMA_CONTROL 0x10 |
#define | MEC_DMA_TX_INT_ENABLE 0x0000000000000001 |
#define | MEC_DMA_TX_DMA_ENABLE 0x0000000000000002 |
#define | MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c |
#define | MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0 |
#define | MEC_DMA_RX_INT_THRESH_SHIFT 4 |
#define | MEC_DMA_RX_INT_ENABLE 0x0000000000000200 |
#define | MEC_DMA_RX_RUNT 0x0000000000000400 |
#define | MEC_DMA_RX_PACKET_GATHER 0x0000000000000800 |
#define | MEC_DMA_RX_DMA_OFFSET 0x0000000000007000 |
#define | MEC_DMA_RX_DMA_OFFSET_SHIFT 12 |
#define | MEC_DMA_RX_DMA_ENABLE 0x0000000000008000 |
#define | MEC_TIMER 0x18 |
#define | MEC_TX_ALIAS 0x20 |
#define | MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001 |
#define | MEC_RX_ALIAS 0x28 |
#define | MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200 |
#define | MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0 |
#define | MEC_TX_RING_PTR 0x30 |
#define | MEC_TX_RING_WRITE_PTR 0x00000000000001ff |
#define | MEC_TX_RING_READ_PTR 0x0000000001ff0000 |
#define | MEC_TX_RING_PTR_ALIAS 0x38 |
#define | MEC_RX_FIFO 0x40 |
#define | MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f |
#define | MEC_RX_FIFO_READ_PTR 0x0000000000000f00 |
#define | MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000 |
#define | MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000 |
#define | MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000 |
#define | MEC_RX_FIFO_ALIAS1 0x48 |
#define | MEC_RX_FIFO_ALIAS2 0x50 |
#define | MEC_TX_VECTOR 0x58 |
#define | MEC_IRQ_VECTOR 0x58 |
#define | MEC_PHY_DATA 0x60 |
#define | MEC_PHY_DATA_BUSY 0x00010000 |
#define | MEC_PHY_DATA_VALUE 0x0000ffff |
#define | MEC_PHY_ADDRESS 0x68 |
#define | MEC_PHY_ADDR_REGISTER 0x0000001f |
#define | MEC_PHY_ADDR_DEVICE 0x000003e0 |
#define | MEC_PHY_ADDR_DEVSHIFT 5 |
#define | MEC_PHY_READ_INITIATE 0x70 |
#define | MEC_PHY_BACKOFF 0x78 |
#define | MEC_STATION 0xa0 |
#define | MEC_STATION_ALT 0xa8 |
#define | MEC_STATION_MASK 0x0000ffffffffffffULL |
#define | MEC_MULTICAST 0xb0 |
#define | MEC_TX_RING_BASE 0xb8 |
#define | MEC_TX_PKT1_CMD_1 0xc0 |
#define | MEC_TX_PKT1_BUFFER_1 0xc8 |
#define | MEC_TX_PKT1_BUFFER_2 0xd0 |
#define | MEC_TX_PKT1_BUFFER_3 0xd8 |
#define | MEC_TX_PKT2_CMD_1 0xe0 |
#define | MEC_TX_PKT2_BUFFER_1 0xe8 |
#define | MEC_TX_PKT2_BUFFER_2 0xf0 |
#define | MEC_TX_PKT2_BUFFER_3 0xf8 |
#define | MEC_MCL_RX_FIFO 0x100 |
#define MEC_DMA_CONTROL 0x10 |
Definition at line 88 of file if_mecreg.h.
#define MEC_DMA_RX_DMA_ENABLE 0x0000000000008000 |
Definition at line 99 of file if_mecreg.h.
#define MEC_DMA_RX_DMA_OFFSET 0x0000000000007000 |
Definition at line 97 of file if_mecreg.h.
#define MEC_DMA_RX_DMA_OFFSET_SHIFT 12 |
Definition at line 98 of file if_mecreg.h.
#define MEC_DMA_RX_INT_ENABLE 0x0000000000000200 |
Definition at line 94 of file if_mecreg.h.
#define MEC_DMA_RX_INT_THRESH_SHIFT 4 |
Definition at line 93 of file if_mecreg.h.
#define MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0 |
Definition at line 92 of file if_mecreg.h.
#define MEC_DMA_RX_PACKET_GATHER 0x0000000000000800 |
Definition at line 96 of file if_mecreg.h.
#define MEC_DMA_RX_RUNT 0x0000000000000400 |
Definition at line 95 of file if_mecreg.h.
#define MEC_DMA_TX_DMA_ENABLE 0x0000000000000002 |
Definition at line 90 of file if_mecreg.h.
#define MEC_DMA_TX_INT_ENABLE 0x0000000000000001 |
Definition at line 89 of file if_mecreg.h.
#define MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c |
Definition at line 91 of file if_mecreg.h.
#define MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000 |
Definition at line 86 of file if_mecreg.h.
#define MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080 |
Definition at line 80 of file if_mecreg.h.
#define MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040 |
Definition at line 79 of file if_mecreg.h.
#define MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00 |
Definition at line 81 of file if_mecreg.h.
#define MEC_INT_RX_MCL_FIFO_SHIFT 8 |
Definition at line 82 of file if_mecreg.h.
#define MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000 |
Definition at line 85 of file if_mecreg.h.
#define MEC_INT_RX_THRESHOLD 0x0000000000000020 |
Definition at line 78 of file if_mecreg.h.
#define MEC_INT_STATUS 0x08 |
Definition at line 71 of file if_mecreg.h.
#define MEC_INT_STATUS_MASK 0x00000000000000ff |
Definition at line 72 of file if_mecreg.h.
#define MEC_INT_TX_ABORT 0x0000000000000010 |
Definition at line 77 of file if_mecreg.h.
#define MEC_INT_TX_EMPTY 0x0000000000000001 |
Definition at line 73 of file if_mecreg.h.
#define MEC_INT_TX_LINK_FAIL 0x0000000000000004 |
Definition at line 75 of file if_mecreg.h.
#define MEC_INT_TX_MEM_ERROR 0x0000000000000008 |
Definition at line 76 of file if_mecreg.h.
#define MEC_INT_TX_PACKET_SENT 0x0000000000000002 |
Definition at line 74 of file if_mecreg.h.
#define MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000 |
Definition at line 83 of file if_mecreg.h.
#define MEC_INT_TX_RING_BUFFER_SHIFT 16 |
Definition at line 84 of file if_mecreg.h.
#define MEC_IRQ_VECTOR 0x58 |
Definition at line 124 of file if_mecreg.h.
#define MEC_MAC_CONTROL 0x00 |
Definition at line 45 of file if_mecreg.h.
#define MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */ |
Definition at line 46 of file if_mecreg.h.
#define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040 |
Definition at line 54 of file if_mecreg.h.
#define MEC_MAC_FILTER_MASK 0x0000000000000060 |
Definition at line 51 of file if_mecreg.h.
#define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020 |
Definition at line 53 of file if_mecreg.h.
#define MEC_MAC_FILTER_PROMISC 0x0000000000000060 |
Definition at line 55 of file if_mecreg.h.
#define MEC_MAC_FILTER_STATION 0x0000000000000000 |
Definition at line 52 of file if_mecreg.h.
#define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */ |
Definition at line 47 of file if_mecreg.h.
#define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */ |
Definition at line 48 of file if_mecreg.h.
#define MEC_MAC_IPG_DEFAULT |
Definition at line 66 of file if_mecreg.h.
#define MEC_MAC_IPGR1 0x00000000003f8000 |
Definition at line 59 of file if_mecreg.h.
#define MEC_MAC_IPGR1_SHIFT 15 |
Definition at line 60 of file if_mecreg.h.
#define MEC_MAC_IPGR2 0x000000001fc00000 |
Definition at line 61 of file if_mecreg.h.
#define MEC_MAC_IPGR2_SHIFT 22 |
Definition at line 62 of file if_mecreg.h.
#define MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */ |
Definition at line 57 of file if_mecreg.h.
#define MEC_MAC_IPGT_SHIFT 8 |
Definition at line 58 of file if_mecreg.h.
#define MEC_MAC_LINK_FAILURE 0x0000000000000080 |
Definition at line 56 of file if_mecreg.h.
#define MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */ |
Definition at line 50 of file if_mecreg.h.
#define MEC_MAC_REVISION 0x00000000e0000000 |
Definition at line 63 of file if_mecreg.h.
#define MEC_MAC_REVISION_SHIFT 29 |
Definition at line 64 of file if_mecreg.h.
#define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */ |
Definition at line 49 of file if_mecreg.h.
#define MEC_MCL_RX_FIFO 0x100 |
Definition at line 153 of file if_mecreg.h.
#define MEC_MULTICAST 0xb0 |
Definition at line 142 of file if_mecreg.h.
#define MEC_PHY_ADDR_DEVICE 0x000003e0 |
Definition at line 132 of file if_mecreg.h.
#define MEC_PHY_ADDR_DEVSHIFT 5 |
Definition at line 133 of file if_mecreg.h.
#define MEC_PHY_ADDR_REGISTER 0x0000001f |
Definition at line 131 of file if_mecreg.h.
#define MEC_PHY_ADDRESS 0x68 |
Definition at line 130 of file if_mecreg.h.
#define MEC_PHY_BACKOFF 0x78 |
Definition at line 136 of file if_mecreg.h.
#define MEC_PHY_DATA 0x60 |
Definition at line 126 of file if_mecreg.h.
#define MEC_PHY_DATA_BUSY 0x00010000 |
Definition at line 127 of file if_mecreg.h.
#define MEC_PHY_DATA_VALUE 0x0000ffff |
Definition at line 128 of file if_mecreg.h.
#define MEC_PHY_READ_INITIATE 0x70 |
Definition at line 135 of file if_mecreg.h.
#define MEC_RX_ALIAS 0x28 |
Definition at line 105 of file if_mecreg.h.
#define MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200 |
Definition at line 106 of file if_mecreg.h.
#define MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0 |
Definition at line 107 of file if_mecreg.h.
#define MEC_RX_FIFO 0x40 |
Definition at line 114 of file if_mecreg.h.
#define MEC_RX_FIFO_ALIAS1 0x48 |
Definition at line 121 of file if_mecreg.h.
#define MEC_RX_FIFO_ALIAS2 0x50 |
Definition at line 122 of file if_mecreg.h.
#define MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f |
Definition at line 115 of file if_mecreg.h.
#define MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000 |
Definition at line 117 of file if_mecreg.h.
#define MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000 |
Definition at line 119 of file if_mecreg.h.
#define MEC_RX_FIFO_READ_PTR 0x0000000000000f00 |
Definition at line 116 of file if_mecreg.h.
#define MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000 |
Definition at line 118 of file if_mecreg.h.
#define MEC_STATION 0xa0 |
Definition at line 138 of file if_mecreg.h.
#define MEC_STATION_ALT 0xa8 |
Definition at line 139 of file if_mecreg.h.
#define MEC_STATION_MASK 0x0000ffffffffffffULL |
Definition at line 140 of file if_mecreg.h.
#define MEC_TIMER 0x18 |
Definition at line 101 of file if_mecreg.h.
#define MEC_TX_ALIAS 0x20 |
Definition at line 102 of file if_mecreg.h.
#define MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001 |
Definition at line 103 of file if_mecreg.h.
#define MEC_TX_PKT1_BUFFER_1 0xc8 |
Definition at line 145 of file if_mecreg.h.
#define MEC_TX_PKT1_BUFFER_2 0xd0 |
Definition at line 146 of file if_mecreg.h.
#define MEC_TX_PKT1_BUFFER_3 0xd8 |
Definition at line 147 of file if_mecreg.h.
#define MEC_TX_PKT1_CMD_1 0xc0 |
Definition at line 144 of file if_mecreg.h.
#define MEC_TX_PKT2_BUFFER_1 0xe8 |
Definition at line 149 of file if_mecreg.h.
#define MEC_TX_PKT2_BUFFER_2 0xf0 |
Definition at line 150 of file if_mecreg.h.
#define MEC_TX_PKT2_BUFFER_3 0xf8 |
Definition at line 151 of file if_mecreg.h.
#define MEC_TX_PKT2_CMD_1 0xe0 |
Definition at line 148 of file if_mecreg.h.
#define MEC_TX_RING_BASE 0xb8 |
Definition at line 143 of file if_mecreg.h.
#define MEC_TX_RING_PTR 0x30 |
Definition at line 109 of file if_mecreg.h.
#define MEC_TX_RING_PTR_ALIAS 0x38 |
Definition at line 112 of file if_mecreg.h.
#define MEC_TX_RING_READ_PTR 0x0000000001ff0000 |
Definition at line 111 of file if_mecreg.h.
#define MEC_TX_RING_WRITE_PTR 0x00000000000001ff |
Definition at line 110 of file if_mecreg.h.
#define MEC_TX_VECTOR 0x58 |
Definition at line 123 of file if_mecreg.h.