dev_ssc.cc Source File

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dev_ssc.cc
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1 /*
2  * Copyright (C) 2003-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: System Support Chip serial controller
29  *
30  * Serial controller on DECsystem 5400 and 5800.
31  * Known as System Support Chip on VAX 3600 (KA650).
32  *
33  * Described around page 80 in the kn210tm1.pdf.
34  */
35 
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39 
40 #include "console.h"
41 #include "cpu.h"
42 #include "devices.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46 
47 
48 #define RX_INT_ENABLE 0x40
49 #define RX_AVAIL 0x80
50 #define TX_INT_ENABLE 0x40
51 #define TX_READY 0x80
52 
53 #define SSC_TICK_SHIFT 14
54 
55 /*
56  * _TXRX is for debugging putchar/getchar. The other
57  * one is more general.
58  */
59 /* #define SSC_DEBUG_TXRX */
60 #define SSC_DEBUG
61 
62 struct ssc_data {
64  int use_fb;
65 
66  int rx_ctl;
67  int tx_ctl;
68 
69  struct interrupt irq;
70 };
71 
72 
74 {
75  struct ssc_data *d = (struct ssc_data *) extra;
76 
77  d->tx_ctl |= TX_READY; /* transmitter always ready */
78 
79  d->rx_ctl &= ~RX_AVAIL;
81  d->rx_ctl |= RX_AVAIL;
82 
83  /* rx interrupts enabled, and char avail? */
84  if (d->rx_ctl & RX_INT_ENABLE && d->rx_ctl & RX_AVAIL) {
85  /* TODO: This is for 5800 only! */
86  unsigned char txvector = 0xf8;
87  cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
90  }
91 
92  /* tx interrupts enabled? */
93  if (d->tx_ctl & TX_INT_ENABLE) {
94  /* TODO: This is for 5800 only! */
95  unsigned char txvector = 0xfc;
96  cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector,
99  }
100 }
101 
102 
104 {
105  uint64_t idata = 0, odata = 0;
106  struct ssc_data *d = (struct ssc_data *) extra;
107 
108  if (writeflag == MEM_WRITE)
109  idata = memory_readmax64(cpu, data, len);
110 
111  dev_ssc_tick(cpu, extra);
112 
113  switch (relative_addr) {
114  case 0x0080: /* receive status */
115  if (writeflag==MEM_READ) {
116  odata = d->rx_ctl;
117 #ifdef SSC_DEBUG_TXRX
118  debug("[ ssc: read from 0x%08lx: 0x%02x ]\n",
119  (long)relative_addr, (int)odata);
120 #endif
121  } else {
122  d->rx_ctl = idata;
123 
125 
126 #ifdef SSC_DEBUG_TXRX
127  debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
128  (long)relative_addr, (int)idata);
129 #endif
130  }
131 
132  break;
133  case 0x0084: /* receive data */
134  if (writeflag==MEM_READ) {
135 #ifdef SSC_DEBUG_TXRX
136  debug("[ ssc: read from 0x%08lx ]\n",
137  (long)relative_addr);
138 #endif
140  odata = console_readchar(d->console_handle);
141  } else {
142 #ifdef SSC_DEBUG_TXRX
143  debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
144  (long)relative_addr, (int)idata);
145 #endif
146  }
147 
148  break;
149  case 0x0088: /* transmit status */
150  if (writeflag==MEM_READ) {
151  odata = d->tx_ctl;
152 #ifdef SSC_DEBUG_TXRX
153  debug("[ ssc: read from 0x%08lx: 0x%04x ]\n",
154  (long)relative_addr, (int)odata);
155 #endif
156  } else {
157  d->tx_ctl = idata;
158 
160 
161 #ifdef SSC_DEBUG_TXRX
162  debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
163  (long)relative_addr, (int)idata);
164 #endif
165  }
166 
167  break;
168  case 0x008c: /* transmit data */
169  if (writeflag==MEM_READ) {
170  debug("[ ssc: read from 0x%08lx ]\n",
171  (long)relative_addr);
172  } else {
173  /* debug("[ ssc: write to 0x%08lx: 0x%02x ]\n",
174  (long)relative_addr, (int)idata); */
175  console_putchar(d->console_handle, idata);
176  }
177 
178  break;
179  case 0x0100:
180  if (writeflag==MEM_READ) {
181  odata = 128;
182 #ifdef SSC_DEBUG_TXRX
183  debug("[ ssc: read from 0x%08lx: 0x%08lx ]\n",
184  (long)relative_addr, (long)odata);
185 #endif
186  } else {
187 #ifdef SSC_DEBUG_TXRX
188  debug("[ ssc: write to 0x%08lx: 0x%08x ]\n",
189  (long)relative_addr, idata);
190 #endif
191  }
192 
193  break;
194  case 0x0108:
195  if (writeflag==MEM_READ) {
196  debug("[ ssc: read from 0x%08lx ]\n",
197  (long)relative_addr);
198  } else {
199 #ifdef SSC_DEBUG
200  debug("[ ssc: write to 0x%08lx: 0x%08x ]\n",
201  (long)relative_addr, (int)idata);
202 #endif
203  }
204 
205  break;
206  default:
207  if (writeflag==MEM_READ) {
208  debug("[ ssc: read from 0x%08lx ]\n",
209  (long)relative_addr);
210  } else {
211  debug("[ ssc: write to 0x%08lx: 0x%08x ]\n",
212  (long)relative_addr, (int)idata);
213  }
214  }
215 
216  dev_ssc_tick(cpu, extra);
217 
218  if (writeflag == MEM_READ)
219  memory_writemax64(cpu, data, len, odata);
220 
221  return 1;
222 }
223 
224 
225 void dev_ssc_init(struct machine *machine, struct memory *mem,
226  uint64_t baseaddr, const char *irq_path, int use_fb)
227 {
228  struct ssc_data *d;
229 
230  CHECK_ALLOCATION(d = (struct ssc_data *) malloc(sizeof(struct ssc_data)));
231  memset(d, 0, sizeof(struct ssc_data));
232 
233  d->use_fb = use_fb;
235 
236  INTERRUPT_CONNECT(irq_path, d->irq);
237 
238  memory_device_register(mem, "ssc", baseaddr, DEV_SSC_LENGTH,
239  dev_ssc_access, d, DM_DEFAULT, NULL);
240 
242 }
243 
data
u_short data
Definition: siireg.h:79
console_putchar
void console_putchar(int handle, int ch)
Definition: console.cc:410
INTERRUPT_CONNECT
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
INTERRUPT_ASSERT
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
memory
Definition: memory.h:75
debug
#define debug
Definition: dev_adb.cc:57
TX_READY
#define TX_READY
Definition: dev_ssc.cc:51
ssc_data::use_fb
int use_fb
Definition: dev_ssc.cc:64
if
addr & if(addr >=0x24 &&page !=NULL)
Definition: tmp_arm_multi.cc:56
RX_AVAIL
#define RX_AVAIL
Definition: dev_ssc.cc:49
memory_device_register
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
MEM_READ
#define MEM_READ
Definition: memory.h:116
RX_INT_ENABLE
#define RX_INT_ENABLE
Definition: dev_ssc.cc:48
DM_DEFAULT
#define DM_DEFAULT
Definition: memory.h:130
console.h
console_charavail
int console_charavail(int handle)
Definition: console.cc:347
MEM_WRITE
#define MEM_WRITE
Definition: memory.h:117
machine_add_tickfunction
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
ssc_data
Definition: dev_ssc.cc:62
PHYSICAL
#define PHYSICAL
Definition: memory.h:126
misc.h
memory_readmax64
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
machine.h
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Definition: machine.h:97
console_readchar
int console_readchar(int handle)
Definition: console.cc:390
dev_ssc_init
void dev_ssc_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, const char *irq_path, int use_fb)
Definition: dev_ssc.cc:225
TX_INT_ENABLE
#define TX_INT_ENABLE
Definition: dev_ssc.cc:50
console_start_slave
int console_start_slave(struct machine *machine, const char *consolename, int use_for_input)
Definition: console.cc:673
cpu.h
ssc_data::console_handle
int console_handle
Definition: dev_ssc.cc:63
DEV_SSC_LENGTH
#define DEV_SSC_LENGTH
Definition: devices.h:480
cpu::mem
struct memory * mem
Definition: cpu.h:362
NO_EXCEPTIONS
#define NO_EXCEPTIONS
Definition: memory.h:125
ssc_data::irq
struct interrupt irq
Definition: dev_ssc.cc:69
INTERRUPT_DEASSERT
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75
dev_ssc_access
int dev_ssc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
interrupt
Definition: interrupt.h:36
memory_writemax64
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
ssc_data::rx_ctl
int rx_ctl
Definition: dev_ssc.cc:66
devices.h
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Definition: cpu.h:326
ssc_data::tx_ctl
int tx_ctl
Definition: dev_ssc.cc:67
cpu::memory_rw
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
Definition: cpu.h:368
DEVICE_ACCESS
DEVICE_ACCESS(ssc)
Definition: dev_ssc.cc:103
memory.h
SSC_TICK_SHIFT
#define SSC_TICK_SHIFT
Definition: dev_ssc.cc:53
DEVICE_TICK
DEVICE_TICK(ssc)
Definition: dev_ssc.cc:73
CHECK_ALLOCATION
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239

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